Cordless telephone system

ABSTRACT

A cordless telephone system includes a control unit having a speaker, a microphone and control circuitry for selective operation in a &#34;normal&#34; mode for communications between the handset and an outside party, a &#34;local answer&#34; mode for communications between a party at the control unit and an outside party, an &#34;intercom&#34; mode for communications between parties at the control unit and the handset and a &#34;3-way&#34; mode for communications between parties at the control unit and handset and an outside party. A microprocessor so responds to ring detect, control and switch-generated interrupt signals as to obtain the desired communications.

This invention relates to a system which has many features usable advantageously in other types of systems while being especially desirable in a cordless telephone system as disclosed. The system provides high quality transmission and reproduction of audio signals and accurate and reliable transmission of security and digital signals and it is operable over an extended distance range without using excessive power or creating interference. It also incorporates many features to make it more convenient and desirable for the user, including the storage of local, long distance and private carrier numbers for automatic dialing, the use of control and handset units for intercom and three-way conversations, and the provision of a two-line interface. The system is economically manufacturable while being durable and highly reliable with excellent performance.

BACKGROUND OF THE INVENTION

Prior cordless telephone systems have had a number of problems and have been limited with respect to automatic dialing and other features provided for the user. Many of the problems have been related to the need to operate at very low power levels to avoid interference with the reception of radio and television signals by others. The quality of reproduction of audio signals has often been poor and there have been many problems with disruptions of transmissions and fading, with inadequate transmission of dialing signals, and with the dialing of wrong numbers, false ringing and failures to go on hook after completion of a conversation. Unauthorized access has also been a problem.

SUMMARY OF THE INVENTION

This invention was evolved with the general object of providing a system for accurate and reliable transmission of audio and digital signals, particularly for cordless telephone or other systems which must operate in situations in which the relative noise levels are quite high.

Another object of the invention is to provide a cordless telephone system having a high degree of security against unauthorized access and in which the user has many different available modes of operation, with respect to programming, automatic dialing, multiline operation, hold operation and intercom communications.

A further object of the invention is to obtain improved reliability and to prevent malfunctions and failures in operation, especially in systems such as cordless telephone systems having a portable battery operated handset or the like.

Still another object of the invention is to provide a high performance system which is economically manufacturable and also durable and very reliable.

Important features relate to the transmission of a handshake signal after validation of a received signal and the transmission of series of signals having a predetermined value to acknowledge receipt of the handshake signal.

A DTMF chip is provided for permitting touch tone dialing, when desired, and it also performs a variety of additional important functions including the generation of signals which are transmitted to the handset to signal the reception of transmitted digits, the transmission of a signal for a reconstructed ring tone in the handset and the generation of ring/call signals at the control unit speaker.

A speaker is provided in the control unit together with a microphone and voice-operated switching circuitry is provided to allow the control unit to be used as a speaker phone and for intercom communication with the handset as well in three-way conversations.

A specific feature relates to the provision of control circuitry operative to facilitate use of the control unit for communications. For example, it is found that in a local answer mode it is desirable to inhibit transmission of signals from the handset to the outside line and the control circuitry operates to inhibit such transmission and to perform other functions which were discovered or recognized as being desirable.

Another specific feature relates to the use of microprocessor with an interrupt circuit which operates in response to a signal from the handset or a signal from an intercom switch or a signal froma ring detect circuit. With this feature, control operations are effected in accordance with the identity of the signal which caused the interrupt and in accordance with the status of the control unit, permitting priority handling of signals as required or desired for optimum communications.

Additional important features relate to the provision of a two line interface circuit and the provision for switching from one line to the other, together with the provision of hold controls for hold of a signal on one line, the handset being usable for control of such functions.

These and other objects, features and advantages of the invention will become more fully apparent from the following detailed description taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a perspective view showing a base or control unit and a handset cradled thereon, constructed in accordance with the invention;

FIG. 2 is a perspective view of the control unit, from a different viewing angle and with the handset removed;

FIG. 3 is a perspective view of the handset, showing the keys and other elements on one side of the handset which are not visible in the cradled position of FIG. 1;

FIG. 4 is another perspective view of the control unit, showing the appearance of the underside thereof and also showing the antenna of the control unit and switch controls which are not visible in the normal position of the control unit;

FIG. 5 is a schematic block diagram of the electrical circuitry of the control unit;

FIG. 6 is a schematic block diagram of the circuitry of the handset;

FIG. 7 is a schematic circuitry of the transmitter and receiver sections of the control unit and an isolation circuit thereof;

FIG. 8 is a schematic block diagram showing the key functional elements of digital signal detector and processing circuitry of the control unit;

FIG. 9 is a circuit diagram of switching and control circuitry of the control unit;

FIG. 10 is a circuit diagram of a switching circuit of the control unit;

FIG. 11 is a schematic diagram of microphone amplifier and voice-operated control circuitry of the control unit;

FIG. 12 is a circuit diagram of interrupt circuitry of the control unit;

FIG. 13 is a circuit diagram of processor, memory, tone generator and control circuitry of the control unit;

FIG. 14 is a circuit diagram of a Schmitt trigger circuit of the unit;

FIG. 15 is a circuit diagram of a 83 Hz detector circuit of the control unit;

FIG. 16 is a circuit diagram of 98 Hz detector and filter circuits of the control unit;

FIG. 17 is a circuit diagram of a gate circuit of the control unit;

FIG. 18 is a circuit diagram of a line circuit of the control unit;

FIG. 19 is a circuit diagram of a power supply circuit of control unit;

FIG. 20 is a circuit diagram showing ring detect and two line interface circuits of the control unit;

FIG. 21 is a a block diagram of a microcomputer used in the control unit;

FIG. 22 is a memory map showing the use of general purpose registers of the microcomputer of FIG. 21 in the system of the invention;

FIG. 23 is a flow chart illustrating the general operation of the microcomputer in the system of the invention;

FIG. 24 is a flow chart illustrating interrupt processing in the system of the invention;

FIG. 25 is a flow chart illustrating "ESCAPE" operations in the system;

FIG. 26 is a flow chart illustrating certain "KEYRED" and related operations in the system;

FIG. 27 is a flow chart illustrating the detection of low-to-high signal transitions in the system of the invention;

FIG. 28 is a flow chart illustrating certain "KEYTEST" and "REDUND" operations in the system of the invention;

FIG. 29 is a flow chart illustrating a certain "VERIFY SECURITY" operation of the system of the invention;

FIG. 30 is a flow chart illustrating certain "TALK JUMP" and "TALKMODE" operations of the systems of the invention;

FIG. 31 is a flow chart showing initialization operations of the system of the invention;

FIG. 32, is a flow chart illustrating certain control unit switch check operations of the system of the invention;

FIG. 33 is a flow chart illustration certain loss of signal or "LOS" operations during the "ESCAPE" operations illustrated in FIG. 25;

FIG. 34 is a flow chart illustrating certain "INTERCOM" operations which may performed during the "ESCAPE" operation of FIG. 25;

FIG. 35 is a flow chart illustrating certain "TOUT" operations which may be performed during the "ESCAPE" operation of FIG. 25;

FIGS. 36-42 are flow charts illustrating certain "TALK JUMP" operations which may be performed in response to the storage of certain vectors prior to execution of the "TALK JUMP" mode;

FIG. 43 is a circuit diagram of handset 12.

FIG. 44 is a circuit diagram of the low battery detector.

FIG. 45 and 46 are flow charts illustrating the operation of handset 12.

DESCRIPTION OF A PREFERRED EMBODIMENT

Reference numeral 10 generally designates telephone apparatus constructed in accordance with the principles of this invention. The apparatus 10 includes a control unit 11 which is arranged to be connected to one or two telephone lines and also to a 120-volt AC supply. A handset 12 may be cradled on the control unit 11, when not in use, and may be lifted and carried to a remote location for radio communication with the control unit 11. The handset includes an extendable antenna 13 and a similar antenna is provided on the control unit 11.

The control unit 11 has a built-in speaker, mounted behind a perforated wall portion 14 of a housing 15 and also includes a microphone mounted behind an opening 16 in the housing 15. When the handset is at a remote position, the speaker and microphone may be used in answering an incoming call and they may also be used in an intercom mode for communication with the handset. A three-way conversation is also possible.

Control and signalling means are provided on the control unit 11, including a line select button 18 for switching from one telephone line to another. Two lights 19 and 20 are provided for indicating which line is in use.

A hold button 21 is provided which may be pressed to put an incoming call on hold, and which may be pressed again to return to the call or to put the call through to the handset. Light 22 is energized when a call is on hold. An intercom call switch 23 is provided which may be pressed to call the handset for intercom communication therewith, a light 24 being associated with the button 23. An answer button 25 and an associated light 26 are provided for use in answering incoming calls from the control unit 11. Button 25 may be pressed to answer calls and may be pressed again when the call is complete to disconnect from the line. A volume control knob 27 is provided for controlling the volume of the output signal from the speaker.

The handset 12 includes a microphone mounted behind openings 28 in a case 29 and a speaker which is mounted behind a perforated wall portion 30 of the case 29. In addition, a separate ringer speaker is provided which is mounted behind openings in a wall portion 31 of the case 29, wall portion 31 being on the outside of the case, i.e., on a portion of the case which faces outwardly away from the ear when the wall portion 30 is held against the ear of the user. The separate ringer speaker thus obviates the possibility of applying a strong ringing signal directly to the ear.

The handset 12 has a number of controls. A two level volume control 32 is provided and an OFF/ON/TALK control 33 is provided. In the off position of control 33, the handset 12 will not receive calls and cannot be used to make calls. In the ON position of control 33, it can be used to receive calls and in the TALK position of control 33, it may be used to make calls as well as to communicate with the control unit and an outside call. The handset further includes a standard type of pushbutton key pad 34 with 12 keys for the numbers 0 through 9 and the symbols asterisk (*), and octothorpe (#).

The asterisk (*) key in an autodial mode is usable as a toll-dialing key and may be used to dial a 28 digit number. When used in conjunction with other automatic dialing features, it provides up to 49 digits to easily access alternative long distance carriers or services.

The octothorpe (#) key in the autodial mode functions as a pause key to provide an automatic three second dialing pause each time the button is pressed when storing an autodial number. Multiple pauses can be programmed to achieve a longer pause. Both the asterisk (*) and octothorpe (#) keys also function to produce the designated DTMF tones when not in the autodial mode and when DTMF dialing is selected at the central unit.

The handset 12 also includes a handset line advance or "LINE" key 35 which is usable to select either of the external phone lines connected to the control unit 11. A HOOK/FLASH key 36 is provided to allow recalling of dial tone without turning off the phone. It permits use in phone systems requiring "flash" for call transfer, conference calls, "call waiting", and other custom services. A HOLD key 37 is provided for putting an incoming call on hold. It may be pressed again to return to the call or to put the call through to the control unit 11.

An automatic dial or "AUTODIAL" key 38 is provided for automatically redialing the last number called and for automatically dialing a number stored in memory. An INTERCOM key 39 is provided which may be pressed to call the control unit 11 for intercom communication therewith.

A "STORE" key 40 is provided for allowing the user to store into memory any of ten numbers with up to 22 digits in each number, or store into memory a toll-dialing number with up to 28 digits. Pauses of three seconds may be stored in the autodial number by pressing the octothorpe (#) key. More than one pause may be stored. However, each three second pause counts as one digit in storage memory.

The handset 12 further includes a mute bar 42 adjacent the microphone openings 28. When pressed, the microphone is momentarily disconnected to allow the user to talk privately without disconnecting from the other party.

The handset 12 includes a rechargeable battery for supplying power to the various circuits thereof. To charge the battery, two contacts 43 and 44 of the handset 12 are engaged with pins 45 and 46 of the control unit 11 when the handset is placed in a cradled position on the control unit 11.

Full duplex communication between the control unit 11 and handset 12 is obtained by frequency modulation and demodulation of 46/49 MHz pairs of FCC-designated channels. Four sets of crystals are provided for selective control of the frequency of the transmitter and receiver of each unit so that if there is a user nearby operating on the same channel pair, a different channel pair may be selected. As shown in FIG. 4, the control unit 11 has a multichannel switch control 47 and a similar control is provided in the handset 12.

An important feature relates to the provision of a programmable security system. Different codes can be programmed into a non-volatile memory in the control unit 11, using the handset pushbuttons. The user chooses his own personal security code to prevent unauthorized outside access to his telephone line or lines.

To change the security code, the control unit 11 is turned over to a position as shown in FIG. 4 and a code switch control 50 is moved to a "code" position. Then a phone number plate 51 on the handset 12 is removed to expose a code select pushbutton 52, as shown in FIG. 3. With the control 33 of the handset in the ON position, the user holds the pushbutton 52 depressed, using a ball-point pen, while entering the new code using the keys 34. He or she enters three digits of his or her choice. When each digit is entered, a confirmation tone is generated. Then the button 52 is released, the plate 51 is replaced, and the control 50 on the base unit is moved to a "telephone" position. Any one of the twelve keys of the key pad 34, the "LINE" key 35, the "HOLD" key 37 or the "INTERCOM" key 39 may be used to enter a digit of the security code. Thus, 3375 security codes are possible.

The apparatus is compatible with tone (DTMF) and also with ten and twenty pulse-per-second rotary dial systems. A selector switch control 53 is provided on the bottom of the control unit 11 to be set in accordance with the type of system to which the apparatus is connected.

The control unit 11 further includes a power light 55, to indicate when power is supplied to the unit, and a charge light 56 which is energized when the battery of the handset 12 is being charged.

In operation, the control unit 11 is connected to a telephone line or lines and also to a power outlet. Batteries of the handset 12 are charged by placing it in the control unit for a sufficient time. Then the handset 12 may be removed from the control unit 11 and the telescoping antenna 13 may be extended. Then while holding the handset 12 and with the control unit 11 in view, the operation of the system may be checked. The power indicator light 55 of the control unit 11 should be energized. Then the OFF/ON/TALK switch control 33 on the handset 12 may be placed in the TALK position. One of the lights 19 or 20 will be energized, indicating that the handset is in use on that line. If the handset line advance button 35 on the handset 12 is pressed, or if while the handset is not in use, the line select control 18 on the control unit 11 is pressed, the line indicator lights 19 and 20 will change to an opposite condition. At this time, a dial tone will be heard through the speaker of the handset 12 as well as through the speaker of the control unit 11.

Then the OFF/ON/TALK control 33 may be placed in the TALK position and the range of operation of the apparatus may be checked. When moving several hundred feet away from the control unit, a dial tone will be heard and an audible system response signal will be heard when any one of the numbered keys of the key set 34 is pressed. This system response signal is an "in-range" signal, indicating that the user is within the operating range of the system and that calls can be received and placed.

To receive calls at the handset 12, the control 33 may be placed in the ON position such that when a call on either line is received, the handset will emit an audible ring signal. Then the control 33 may be placed in the TALK position and the handset may be used in a conventional fashion. When the call is ended, the switch control 33 is placed in the ON condition, to place the handset in condition to receive a subsequent call.

To place a call, the control 33 is placed in the TALK position and the number one line will initially become active. If the user wishes to use the number two line, the line advance or "LINE" key 35 is pressed once. After waiting for a dial tone, the user selects the desired number by slowly pressing the proper keyboard buttons. If an error is made, the HOOK/FLASH button 36 is pressed to regain dial tone. If a busy signal is received or if there is no answer, the HOOK/FLASH button 36 may be pressed or the control 33 may be switched to ON and then back to TALK. Then the automatic redial button 38 may be pressed to cause the last number dialed to be automatically redialed.

The apparatus is designed for use in commercial systems such as those in which a call may be transferred to another line within a private exchange by depressing the hook switch. The HOOK/FLASH button 36 is usable in such systems in the same way as the "hook switch" of a standard telephone set.

The HOLD button 37 may be pressed once to place a call on hold and once again to return to the call. To place the line being used on hold and answer a call on the other line, the hold button 37 may be pressed once and then the line advance key 35 may be pressed to select the alternate line. When the call is completed on the second line, the key 35 may be pressed to regain the original line and then the hold key 37 may be pressed to communicate with the original line.

The control unit 11 may be used as an answering phone completely independent of the handset 12 and may be also used for intercom communication with the handset 12. To receive a call at the control unit 11, the answer button 24 is pressed and then the control unit operates as a "speaker phone". The volume of the speaker of the control unit may be controlled by rotating the control 26 which may be rotated fully counterclockwise to turn the speaker off completely.

To call the control unit 11 from the handset, the control 33 is placed in the talk position and the intercom control 39 is pressed to signal the control unit 11. The person at the control unit 11 may then answer by pushing the intercom call button 23 and then normal intercom communications may be made. Communication may be terminated at the handset by placing the control 33 in the on or off position, or by pressing the "HOOK" key. In addition, it may be terminated at the control unit 11 by pressing the intercom control switch 22.

To receive a call and then use the intercom feature, the handset 12 is used to receive a call and then the hold button 37 is pressed to put the call on hold. Then the intercom button 39 is pressed to call the control unit and the user at the control unit may answer by pressing the intercom/call button 22. Either the handset 12 or the control unit 11 may be used to terminate the intercom function and the other unit may then be used to communicate with the outside party. After the communication in the intercom mode is terminated and the handset is to be used to communicate with the outside party, the HOLD button 37 at the handset 12 is pressed to enable communication with the outside party on the line. If the control unit 11 is to be used to communicate with the outside party, the handset 11 is terminated by placing the control 33 in the on position after which the local answer button 25 and hold button 21 at the control unit are pressed to activate the control unit speaker phone operation and remove the line from hold.

An auto-dial memory system is provided for automatically dialing any of 12 telephone numbers programmed into the memory within the control unit 11. Each of the numbered keys of the group 34 may be used in storing up to a 22 digit number. The asterisk (*) key is usable in storing a number having up to 28 digits and is labeled as a "TOLL" key. It makes possible storing of the code numbers required when using the various private carrier long distance services. The octothorpe (#) key is usable for programming of a delay which is preferably about three seconds. The operation obtained through this key is an important feature. When using a long distance service, there is usually a delay after an access code number has been entered and a second dial tone is heard. There is also a delay in some business telephone systems before a second dial tone is heard when accessing an outside line. Pressing the octothorpe (#) or pause key will cause the control unit to delay before continuing to dial a number. If necessary, two or more delays can be entered to provide a total delay of six or more seconds, for example.

Another feature relates to the generation of an audible "key-confirming" tone each time a key stroke is effected and properly entered. Also, if an error is made in a programming sequence, an audible error signal, in the form of three consecutive beeps, is heard.

To program a local or long distance number, the control 33 is placed in the talk position and the store key 40 is pressed. Next, the desired memory location is entered. For example, the number 5 key may be pressed. Next, the desired telephone number is entered either as a local number or as a long distance number. In programming a long distance number, for example, the initial digit may be "1⃡, under present long distance practice. After the telephone number is entered, the store key 40 is again pressed to load the number into memory.

The toll or asterisk (*) key may be used for automatic dialing of the number of a long distance service and the user's access code number for that service. It can also be used for the complete automatic dialing of a particular long distance number through a long distance service. To program using the toll or asterisk (*) key, the control 33 is placed in the talk position and then the store key 40 is pressed. Then the toll key is pressed. Then the access number of the long distance service is entered, including the area code of the access number, if any, followed by a pause which is entered by depressing the pause or octothorpe (#) key.

Next, the user's access code for the long distance service is entered. This sequence may optionally be followed by entry of a particular long distance number which the user may desire to have automatically dialed through use of the toll key alone.

In using the automatic dialing functions, a local or long distance number may be automatically dialed by placing the switch 33 in the talk position, then pressing the automatic dialing key 40 and then pressing the number key of the desired number. To use the toll (*) key in automatically dialing a long distance number which has been stored for a recall through use of one of the numbered keys, the control 33 is placed in the talk position, the automatic dialing key 40 is pressed, then the toll (*) key is pressed and then the number key of the desired number is pressed.

When a particular long distance number has been entered for automatic dialing through use of the toll key, it is only necessary to place the control 33 in the talk position, then press the automatic dialing key 40 and then press the toll (*) key. The system will then carry out all of the automatic dialing functions required for dialing of the desired long distance number through a long distance service.

The autodial capability also includes means to automatically dial the long distance service dialing sequence while a destination number is entered from the keyboard. Press autodial, *, /. The access and user code numbers will automatically be dialed; then the system will accept any quantity of numbers to be entered from the keyboard. When the destination number has been dialed, the user presses autodial again. The autodial sequence will be completed.

GENERAL DESCRIPTION OF CONTROL UNIT CIRCUITS (FIG. 5)

FIG. 5 is a schematic block diagram of the circuitry of the control unit 11. An indicating and switching circuit board 60 is provided which has terminals numbered 1 through 19 and which is mounted under the top wall of the case 15 of the unit 11. The circuit board 60 supports various switches and indicator lights of the unit as well as a speaker 61, a speaker amplifier 62 and a potentiometer 63 which is controlled by the volume control knob 26. The line 1 and line 2 indicator lights 19 and 20 as well as the hold, intercom, local answer, power and charge indicator lights 22, 24, 26, 55 and 56 are in the form of light-emitting diodes. An additional light-emitting diode 64 may optionally be provided for use when the apparatus is to be used with a single telephone line only. In that case, the light 64 is an "in use" light which indicates that the apparatus is in operation.

A hold switch 65, operated by the hold button 21, is connected between the illustrated terminals 4 and 6. A switch 66, operated by the line select button 18, is connected between terminals 5 and 6. An intercom switch 67, operated by the intercom button 23, is connected between terminal 7 and ground, a capacitor 68 being connected in parallel with the switch 67. A switch 70 operated by the local answer button 25, has a movable contact connected to ground and fixed contacts connected to terminals 11 and 18. Driver circuitry 72 is provided for energizing the lightemitting diode 26 when the local answer switch 70 is in a local position and for energizing diodes 19, 20, 22, 24 and 64 when terminals 1, 2, 10, 8 and 9, respectively, are grounded. Circuitry 72 is supplied with +5 volts from terminal 19. The power-light diode 55 is connected in series with a resistor 73 to terminal 17 which supplies +10 unregulated voltage to the speaker amplifier 62 and also to a charge control circuit 74 which is connected to the charge terminals 45 and 46 as well as the charge indicating diode 56.

The control unit 11 includes an isolation circuit 80 which is connected to an antenna 81 and through a line 82 to the output of a transmitter section 83 and also through a line 84 to the input of a receiver section 85. Isolation circuit 80 operates to minimize transmission between the output of the transmitter 83 and the input of the receiver 85 and it forms an important feature of the invention, as hereinafter described.

The control unit 11 also includes control and signal processing circuitry connected to the transmitter and receiver sections 83 and 85 and also to the indicating and switching circuit board 60. Terminals of the control and signal processing circuitry, indicated schematically by numbered boxes, are connected to the correspondingly numbered terminals of the circuit board 60 as diagrammatically illustrated.

A line circuit 86 is connectable to one or the other of a pair of jacks 87 and 88 and is connected to the output of an outgoing signal amplifier 89 and the input of an incoming signal amplifier 90.

Processor, memory, tone generator and control circuitry is provided, as diagrammatically illustrated by block 92 in FIG. 5. When the apparatus is connected to a telephone system adapted to receive tones, such tones may be supplied to one input of the out-going signal amplifier 89 through a line 93 which is connected through a switching circuit 94 to a tone signal output line 95 of the circuitry 92. A second input of the amplifier 89 is connected through a line 97 and through the switching circuit 94 to a line 98 which is connected to switching and amplifier circuitry 100.

A microphone 101 of the control unit 11 is connected to amplifier and voice operated circuitry 102 which has an output connected through a line 103 to the switching and amplifier circuitry 100. When the control unit 11 is in a local answer mode of operation, amplified signals from the microphone 101 may be applied through the circuitry 100, line 98, circuit 94 and line 97 to an input of the outgoing signal amplifier 89 to be transmitted through the line circuit 86 to an outside line.

The switching and amplifier circuitry 100 is also connected through a line 104 and through a 83 Hz rejection filter 105 and through a line 106 to the output of the receiver section 85, permitting transmission of audio signals to an outside line. Such audio signals may also be applied from the circuitry 100 to terminal number 14 of the circuit board 60, terminal 14 being connected to the potentiometer 63. The movable contact of potentiometer 63 is connected to the input of the amplifier 62 which amplifies an audio signal speaker 61.

For transmission of audio signals from the control unit 11 to the handset 12, a modulation signal input of the transmitter section 83 is connected through a line 108 to the circuitry 100 which, as hereinafter described, includes a summing amplifier one input of which is connectable through switching circuitry to the line 103. Another input is connectable through switching circuitry to a line 109 which is connected to the output of the incoming signal amplifier 90.

Ring detector and gating circuitry 110 is provided, connected through lines 111 and 112 to the jacks 87 and 88. One output of the circuitry 110 is connected through a line 113 to the circuitry 100. Another output is connected through a line 114 to the circuitry 92 and to an interrupt circuit 116 which is connected through a line 117 to the circuitry 92. In response to a ring signal detected on an outside line, the processor and control circuitry 92 is arranged to perform control operations, as determined by the status of the equipment when the ring signal is detected.

For control of operations from the handset 12, digital signal detecting and processing circuitry 118 is provided, having an input connected to the receiver output line 106 and having one output connected to a line 119 which is connected to an input of the interrupt circuit 116 and also to an input of the circuitry 92. To establish communication from the handset 112 to the control unit 11, the handset generates a 83 Hz signal and coded signals as hereinafter described, the 83 Hz signal and the coded signals being detected by the circuitry 118. Among other things, the circuitry 118 develops a "signal present" signal on the line 119 when either the 83 Hz signal or a coded signal is developed. The coded signals are processed and applied through a line 120 to the circuitry 92. The coded signals are, in effect, analyzed by the circuitry 92 and if the signals correspond to a user's code stored in a memory circuit of the circuitry 92, the control unit operates to transmit "handshake" signals and otherwise operates to establish communication with the handset 12.

The circuitry of the control unit 11, as illustrated, includes a two-line interface circuit 122 and it is designed to permit connection to two separate telephone lines. In addition to the "T" and "R" line terminals, a pair of auxiliary terminals may be provided, for use in signalling a switchboard, for transfer of a call to another telephone of a private system or for consultation, three-way calls, etc. The apparatus may, however, be used with a non-commercial type system. For single line operation, the two-line interface circuit 122 may be disconnected and jumpers may be installed as indicated by dotted lines 123 and 124. Also, jumpers, as indicated by dotted lines 125-128, may be installed to permit use of the jack 88 for connection to a telephone accessory such as an answering machine.

A relay 129 is provided which is controlled from the circuitry 92 in a manner as hereinafter described and which has a contact 130 connected in series between the tip or "T" terminal of the operative jack and one input of the line circuit 86. Contact 130 operates as a hook switch and it is controlled by the circuitry 92 to effect pulse-dialing operation, when the apparatus is connected in a telephone system which uses pulse dialing. The type of dialing operation is controlled by the dial select switch control 53 which interconnects terminals of the circuitry 92, as hereinafter described.

Another relay 131 is provided, also operated from the circuitry 92 and having a contact 132 connected in series with a fuse 133 between auxiliary jack terminals. Protective diodes 134 are connected in series with each other and in parallel with the contact 132. Relay 131 and contact 132 are, of course, used only in commercial applications.

A power supply circuit 136 is provided, connected through a line cord 137 to a plug 138. The power supply circuit 136 supplies a +10 regulated voltage on a line 139, a +10 unregulated voltage on a line 140, a +5 regulated voltage on a line 141 and a power-up signal on a line 142. In addition, it supplies a minus 25-volt memory enable signal on a line 143, connected to a non-volatile memory circuit within the circuitry 92.

GENERAL DESCRIPTION OF HANDSET CIRCUITS (FIG. 6)

FIG. 6 is a schematic diagram of the circuitry of the handset 12. An isolation circuit 146 is provided which is connected to the antenna 13 and which is connected through a line 147 to the output of a transmitter section 48 and also through a line 149 to the input of a receiver section 150. A voltage supply input of the receiver section is connected through a line 151 to control and switching circuitry 152 which is connected to a microprocessor 154 to control operation of the receiver section. The output of the receiver section 150 is connected to a line 155 which is connected to a volume control switch in the circuitry 152 and also to an input of a 1633 Hz detector 156, the output of the 1633 Hz detector 156 being applied through a line 157 to the circuitry 152. A control input to the detector 156 is connected through a line 158 to an output of the processor 154 which is also connected through a line 159 to the circuitry 152. When the control 33 of the handset 12 is in its "on" position and a 1633 Hz signal is produced at the output of the receiver 150 and detected by the detector 156, the processor 154 operates to apply a signal through a line 160 to the input of an amplifier 162 connected to a ringer speaker 163. The 1633 Hz detector 156 is also used in detecting "handshake" signals, as hereinafter described.

When the ringer speaker 163 is energized, the user may respond by moving the control 33 to the "TALK" position. Then audio signals developed at the output of the receiver 150 and applied through line 151 to the circuitry 152 are transmitted through a line 165 to the input of an amplifier 166 connected to a main speaker 167 of the handset 12. The user may then hear communications from a party calling from an outside line, or, in the intercom mode, from a person located at the control unit 11.

To provide communication from the user of the handset to an outside party or to a person at the control unit 11, a microphone 170 is provided which is connected to the input of an amplifier 171. The output of the amplifier 171 is connected to one input of a summing amplifier 172 which has an output connected through a line 173 to the transmitter section 148 to frequency modulate the output of the transmitter section 148. Control inputs of the transmitter 148 and amplifier 171 are connected through a line 174 to the control and switching circuitry 152.

To call an outside party from the handset 12, the user moves the control 33 to the "TALK" position and then the processor 154 operates to apply a 83 Hz square wave signal through a line 176 to a 83 Hz filter 177 which is connected through a line 178 to a second input of the summing amplifier 172. The output of the transmitter section 148 is then modulated to send out a substantially sinusoidal 83 Hz burst which signals the control unit. After a 83 Hz burst is sent, the processor develops a 98 Hz coded signal on a line 180 which is applied to a third input of the summing amplifier 172. The coded signal is detected by the control unit and if properly received, the control unit develops a 1633 Hz "handshake" signal which is transmitted back to the handset to be detected by the detector 156. Then the processor operates to develop a 98 Hz coded null signal on the line 180 for transmission by the transmitter section 148. If the null signal is properly detected by the control unit 11, the transmission of the 1633 Hz "handshake" signal is terminated and then the processor 154 responds to the termination of the "hand shake" signal to develop another coded signal on the line 180 for transmission to the control unit, the sequence being repeated.

When the coded signals correspond to a security code stored in the memory of the control unit, the control unit may function to connect to an outside line and to allow transmission of a dial tone signal back to the handset. Then keys of the key set 34 may be used to dial a number to be called, the processor 154 being then operative to develop digital signals on the line 180 corresponding to the dialed digits.

The switches of the key set 34 are located in a keyboard circuit 182 as shown with connections to the processor 154 as shown. When any one of the keys of the key pad 34 or any of the control keys is depressed and there is an acceptance of that key by the control unit, the control unit sends a tone signal to the handset. This tone is detected by the handset 1633 Hz detector which causes the processor to output a beep tone which is applied through resistors 183 and 184 to the input of the speaker amplifier 166. The junction between resistors 183 and 184 is normally clamped to ground through a transistor 185 and a diode 186, the base of the transistor 185 being forwardly biased through a resistor 187. When any one of the keys is depressed, the base of the transistor 185 is grounded through one of four diodes 188 connected to four of the lines of the keyboard matrix.

Power for the handset 12 is supplied by a battery 190 having a grounded negative terminal and having a positive terminal connected through a diode 191 to the charging terminal 44, the other charging terminal 43 being connected to ground. The positive terminal of the battery 190 is connected to a +5 volt line 192 which is connected directly to certain circuits as diagrammatically indicated. As hereinafter described, a switch of the circuitry 152 operates when the control 33 is moved to the "on" or "talk" positions to connect line 192 to a line 193 which is designated as a +5 volt switch line and which is connected to other circuits as indicated.

A battery low detector 194 is connected to the line 192 and also to a line 195 which is connected to the charge terminal 44. The output of the battery low detector 194 is connected through a line 196 to the processor 154. The processor operates to effect transmission of two "beep" tones periodically at 15-second intervals for 15 minutes, followed by 8 beeps in rapid sequence before automatic shutdown. The remaining charge of the battery 190 after shutdown will be sufficient for holding the memory circuits for months.

A power-up circuit 198 is connected to stand by and master clear lines of the processor 154, through lines 199 and 200. Clock circuitry of the processor 154 is connected to a crystal 202 and through a resistor 203 to the +5 volt battery line 192.

The handset 12 further includes a mute circuit 204 which is connected through a line 205 to the microphone amplifier 171. One input of mute circuit 204 is connected through a switch 206 to the +5 volt switch line 193, the switch 206 being operated by the mute bar 42. A second input of the mute circuit 204 is connected through a line 207 to the processor 154.

TRANSMITTER, RECEIVER AND ISOLATION CIRCUITS OF CONTROL UNIT 11 (FIG. 7)

Important features of the invention relate to the coupling of the antenna of each unit to the transmitter and receiver sections thereof in a manner such as to obtain high efficiency and low noise and to obtain a high degree of isolation with respect to detection of transmitted signals in the receiver section. The circuits are such as to be substantially unaffected by variations in loading of the antenna such as those resulting from variations in the position of the antenna relative to the body of the user or other nearby physical structures. The circuits are also advantageous in being relatively simple in construction and in using relatively inexpensive components which are readily interconnected and which are reliable and trouble-free in operation.

FIG. 7 is a circuit diagram of the isolation circuit 80 and transmitter and receiver sections 83 and 85 of the control unit 11. Similar circuits are used in the handset 12.

The transmitter section 83 comprises a transistor 210 which operates as an oscillator to develop a frequency modulated output signal having a center or carrier frequency which is within a narrow output frequency band such as the 46 MHz FCC-allocated band. The exact carrier frequency is controlled by one of four crystals 211-214 having resonate frequencies which are different from each other but which are within a narrow range at 1/3 the narrow output frequency range, a frequency-trebling action being produced in the oscillator circuit. When the user encounters interference, he may switch to a different frequency and ordinarily, at least one of the four available frequencies will be free of interference.

The oscillator circuit includes a tank circuit formed by a capacitor 216 and a primary winding 217 of a coil or transformer 218 which has a secondary winding 219 connected between the output line 82 and ground. A tap of the primary winding 217 is connected to the collector of transistor 210 while one end terminal of primary winding 217 is connected through a zener diode 220 to ground and through a resistor 221 to the power-supply line 139 to which a 10-volt regulated voltage is applied from the power supply 136. The tank circuit formed by capacitor 216 and winding 217 has a resonant frequency at about a mid-frequency of the aforementioned narrow output frequency band and at about three times the resonant frequencies of the crystals 211-214.

The emitter of the transistor 210 is connected to ground through a capacitor 225 and a parallel resistor 226 and is also connected through a capacitor 227 to the base thereof, the base being connected through a resistor 228 to ground. The base is also coupled to the crystals, being connected through a choke coil 229 and a resistor 230 to a line 232 which is connected to terminals of the crystals 211-214 through a group of capacitors 234 formed by four fixed capacitors and four trimmer capacitors in parallel. The other terminals of the crystals 211-214 are connected to fixed switch contacts which are selectively engageable by a movable switch contact 236.

A varactor diode 237 is provided for modulating the transmitted frequency. The switch contact 236 is connected to ground through a varactor diode 237 and through a resistor 239 to the line 108 which is connected through a capacitor 240 to ground. Audio and tone signals are applied to the line 108 from the switching and amplifier circuitry 100. The applied signals operate to vary the effective reactance of the varactor diode 237 to shift the frequency of oscillation in proportion to the magnitude of the signal applied on line 108.

On-off operation of the transmitter section 83 is controlled by a transistor 242 which has its collector connected through a resistor 243 to the base of the transistor 210 with the emitter of transistor 242 being connected to the +5-volt power supply line 141. The base of the transistor 242 is connected through a resistor 245 to the line 141 and is connected through a resistor 246 and through diodes 247 and 248 to two control lines 249. Control lines 249 and 250 are connected to outputs of the circuitry 92. When either of the lines 249 or 250 is brought to a low state, at or near ground potential, the transistor 242 is rendered conductive to apply a positive bias through resistor 243 to the base of the oscillator transistor 210 to cause operation of the oscillator circuit.

The isolation circuit 80 includes antenna coupling means which, in the illustrated arrangement, includes a winding 252 of a matching coil or transformer 253 which has a second winding 254. The antenna coupling means further includes a loading coil 255 connected between one terminal of the coil and the antenna 81, the other terminal of the winding 252 being connected to ground. The antenna may alternatively be coupled through the loading coil 252 to the ungrounded end of winding 254 so as not to use winding 252. Such an arrangement is used in the handset 12.

One terminal of the winding 254 is connected to ground and other terminals thereof are coupled through transmitter and receiver coupling means to the output of the transmitter section 83 and the input of the receiver section 85. The transmitter coupling means includes a capacitor 257 and an inductor 258 connected in series between a tap 259 of the winding 254 and the output line 82 of the transmitter section 83. The receiver coupling means comprises a filter 260 connected between an end terminal 261 of the winding 254 and the receiver input line 84. The filter 260 comprises an inductor 262 connected in series between the terminal 261 and line 84. It further includes a pair of capacitors 263 and 264 connected in series with each other and also in series between terminal 261 and line 84, the series combination of capacitors 263 and 264 being connected in parallel relation to the inductor 262. The filter 260 additionally includes a resistor 265 connected between ground and the junction between capacitors 263 and 264.

The isolation circuitry as shown is comparatively simple and it has a number of features which cooperate to reliably achieve excellent performance over a wide range of operating conditions. The combination of capacitor 257 and inductor 258 provides a series resonant circuit and the resonant frequency thereof is at the mid-frequency of the narrow output frequency band of the transmitter section. As a result, it provides minimum impedance to flow of current at the output frequency and efficient transmission of power to the antenna 81. The combination of capacitor 257 and inductor 258, however, has a high impedance at the receiver frequency which may, for example, be in the 49 MHz band when the transmitter frequency is in the 46 MHz band. Thus, efficient coupling is provided between the transmitter section and the antenna for transmission of signals while loading of the receiver section is very substantially reduced.

The filter 260 is very important in that it provides a further attenuation of high magnitude with respect to transmission of signals from the transmitter section output to the receiver section input. The combination of inductor 262 and capacitors 263 and 264 forms a parallel resonant circuit which is effectively in series relation with respect to transmission of signals from the terminal 261 to the receiver section input line 84. It is tuned to resonate at the transmitter frequency. When, for example, the transmitter frequency is in the 46 MHz range, the filter 260 is tuned to resonate in the 46 MHz range to provide a very high impedance with respect to transmission of transmitted signals to the receiver section input. However, the filter 260 is not resonant at the receiver frequency, which may be in the 49 MHz range when the transmitter frequency is in the 46 MHz range. The filter thereby provides a relatively low impedance with respect to received signals, for efficient coupling thereof.

The performance of the filter 260 is further enhanced by the provision of the resistor 265 between ground and the junction between capacitors 263 and 264. Resistor 265 operates to provide a phase balance such as to obtain an extremely high attenuation at the frequency to which the filter 260 is tuned.

In addition to having the capability of providing a very high attenuation of transmitted signals at the receiver section input, the isolation circuitry 80 is further advantageous in that its operation is substantially unaffected by variations in the loading of the antenna such as caused by variations in the relationship of the antenna to the body of the user. It is noted that although variations in loading of the antenna may affect the impedance between terminal 261 and ground, across the input of the filter section 260, such impedance variations do not affect the operation of the filter 260 to any substantial degree. Such is the case because the inductor 262 and capacitors 263 and 264 operate in effect as a parallel resonant circuit which provides a very high impedance in series relation to the path of signal transmission, augmented by the effect of the resistor 265.

It is advantageous to couple the transmitter output to the tap 259 of the winding 254 while coupling the receiver input to the end terminal 261 of the winding 254 in obtaining an optimum impedance match for efficient transmission of power to the antenna and for efficient transmission of a received signal to the receiver input.

The values of the components are important. By way of example, components 255, 257, 258, 262, 263, 264 and 265 may have values of about 1.8 microhenries, 6 picofarads, 2 microhenries, 0.22 microhenries, 27 pf, 27 pf, and 8200 ohms.

It is also noted that the use of relatively simple transmitter oscillator circuit as shown is advantageous in reducing noise to a minimum level. With the circuit as shown, it is possible to obtain an extremely low noise level and at the same time obtain highly efficient coupling of energy and signals to and from the antenna, and also obtain a very high degree of isolation between the transmitter and receiver sections. It is possible to obtain a 50 decibel isolation at a minimum while operating over a wide range of variations in antenna loading and other operating conditions.

The receiver section 85 includes an input stage using a dual gate MOSFET transistor 270 with one electrode connected to the line 84 which is connected to ground through a tuned circuit formed by an inductor 271 in parallel with a capacitor 272, the tuned circuit being connected in series with an additional inductor 273. Another electrode is connected through a resistor 274 to the power supply line 141 and through a capacitor 275 and a parallel resistor 276 to ground.

Additional electrodes are connected to ground through a resistor 277 and a parallel capacitor 278. An output electrode is connected to a tap of a primary winding 280 of a coupling transformer 281, a capacitor 282 being connected in parallel with the winding 280. An end terminal of the winding 280 is connected to ground through a capacitor 283 and through a resistor 284 to the power supply line 141.

A coupling transformer 281 has a secondary winding 286 which is connected to the input of a first mixer stage 288, coupled to an oscillator stage 289 and to a first IF section 290.

The circuits of the mixer and oscillator stages 288 and 289 as well as the IF section 290 are not illustrated in detail but it will be understood that standard types of circuits may be used. The mixer stage preferably uses a dual gate MOSFET transistor and the oscillator stage 289 preferably uses a circuit similar to that used in the transmitter section 83. As shown, four crystals 291-294 are selectively connectable to the oscillator stage 289 through a switch 295, for control of the received frequency. By way of example, the IF section may operate at a frequency of 10.695 MHz and a ceramic filter may be included in the IF section 290.

The output of the first IF section 290 is applied to a second mixer 298 which is coupled to a second oscillator stage 299 and a second IF section 300, the output of the second IF section 300 being coupled to a demodulator 302 to develop an output signal on the line 106. The circuits of the mixer 298, oscillator 299, IF section 300 and demodulator 302 are not illustrated in detail, it being understood that standard types of circuits may be used. By way of example, the second IF frequency may be 400 KHz and a ceramic filter may be included in the second IF section 300. With double conversion, it is possible to obtain image rejection such that it is not necessary to use special image rejection filter circuitry in the input stage of the receiver section.

DIGITAL SIGNAL DETECTING AND PROCESSING CIRCUITRY OF CONTROL UNIT (FIG. 8)

FIG. 8 is a block diagram illustrating the circuitry 118 of the control unit 11 which operates to detect and process digital signals transmitted from the handset 12 and developed at the output line 106 of the receiver section 85 of the control unit 11. The circuits are described in detail hereinafter.

When the control 33 of the handset 11 is placed in its "talk" position, a 83 Hz pilot tone is tranmitted which is detected by a detector circuit 305. The input of circuit 305 is connected to a circuit point 306 which is connected through a resistor 307 to the line 106, connected to the output of the receiver section 85. The output of detector circuit 305 is connected to a line 308 which is connected to one input of a gate circuit 310, the output of gate circuit 310 being applied through the "signal present" line 119 to an input of the processor circuitry 92 and also to an input of the interrupt circuitry 116. In response to a transition of the signal developed on line 119, an interrupt is applied to the processor circuitry to cause it to initiate a signal decoding operation.

After transmitting the 83 Hz pilot tone for a certain time interval, the handset 12 initiates transmission of groups of pulse signals that are encoded on the handset transmitted signal by FM modulating the carrier, the pulse signals of each group having a 98 Hz repetition rate and each pulse signal having a predetermined duration, which may signal a null or which may correspond either to a digit of a security code, or to a digit of a number to be called or to a control digit. The duration of each of the pulses of the first group of 98 Hz pulses which is tranmitted from the handset corresponds to a first digit of a security code which is stored in a memory section of the circuitry 92. After properly receiving and registering the first digit, the control unit sends a 1633 Hz handshake signal to the handset which responds by sending acknowledgment signals back to the control unit. In the illustrated system, the acknowledgment signals are 98 Hz pulses of minimum duration referred to herein as "null" pulses or signals.

When the control unit detects null pulses or signals, the 1633 Hz handshake signal is turned off and, in response, the handset sends the next security code digit, by sending a second group of 98 Hz pulses with each pulse of the second group having a duration corresponding to the second digit of the stored code. This sequence is repeated for the third digit of the security code and after the three digits are received and verified, additional dialing or control signals are transmitted from the handset to the control unit to be decoded or analyzed in a similar fashion.

The transmission of the 83 Hz tone signal is discontinued during transmission and decoding of the 98 Hz pulses but is thereafter reinstituted and is continued as long as the handset control 33 is in the "talk" position. Thus, the existence of either a 83 Hz signal or 98 Hz pulses indicates that the control 33 is in the "talk" position.

transmission of the 98 Hz signals is detected by a detector 312. Detector 312 has an input connected to the output of a 98 Hz filter 313, the input of filter 313 being connected to the circuit point 306 which is connected through the resistor 307 to the output line 106 from the receiver section 85. The output of detector circuit 312 is applied through a line 314 to a second input of the gate circuit 310 which operates to continue generation of the signal present signal on the line 119 and to allow the processor circuitry 92 to measure the durations of 98 Hz pulses, such pulses being applied thereto through the line 120.

Line 120 is connected to the output of a Schmitt trigger circuit 318 which has one input connected to the line 106 which is the output line of the receiver section 85. A second input of circuit 318 is connected to line 314. A gating circuit 319 is connected to the line 314 from the 98 Hz detector circuit 312 and is connected through a line 320 to the processor circuitry 92 to insure against undesirable interrupts. As described hereinafter, the Schmitt trigger circuit 318 performs an important function in developing pulses having leading and trailing edges developed at threshold levels of the received signal in a manner such as to minimize the effects of noise in the signals transmitted from the handset 12 to the control unit 11.

The 1633 Hz handshake signal is developed by a tone generator section of the circuitry 92, described hereinafter, which operates to generate signals on the tone signal output line 95, connected to the switching circuitry 94. In addition to the 1633 Hz handshake signal, the tone generator section is also usable to transmit DTMF signals for dialing. During the handshake operation, the 1633 Hz signal is applied from the switching circuit 94 through a line 322 to the switching and amplifying circuitry 100, to be transmitted through the line 108 to the modulation input of the transmitter section 83 for transmission to the handset 12.

SWITCHING AND CONTROL CIRCUITRY (FIGS. 9 AND 10)

FIG. 9 illustrates the switching and control circuitry 100 and FIG. 10 illustrates the switching circuit 94. These circuits operate to control transmission of audio signals, including tone signals, from one circuit to another, under control of various control signals applied from the processor circuitry 92, the amplifier and voice operated circuitry 102, the circuit board 60 and other circuits.

The audio input signals to the circuits 94 and 100 include a microphone signal applied through line 103 to the circuitry 100 and derived from the microphone 103 after amplification in the circuitry 102; a handset audio signal applied through line 104 to the circuitry 100 and derived through filter 105 from the line 106 which is connected to the output of the receiver section 85; a line audio signal applied to the circuitry 100 through the line 109, connected to the output of the incoming signal amplifier 90; and tone signals applied through the line 95 to the circuitry 94. A 1633 Hz tone signal is applied from the switching circuitry 94 and through line 322 to the circuitry 100.

The audio output signals from the circuits 94 and 100 include an outgoing line audio signal applied from the circuit 94 through line 97 to the outgoing amplifier 89, the signal being derived through the line 98 from the circuitry 100; an outgoing handset audio signal applied from the circuitry 100 and through line 108 to the modulation input of the transmitter section 83; a speaker audio signal applied through a line 324 to terminal 14 of the circuit board 60 which is connected through the volume control potentiometer 63 to the input of the speaker amplifier 62; a ring signal which is applied through a line 326 to a ring select switch 328, connected to terminal 13 of the circuit board 60; and DTMF signals which may be applied from circuitry 94 and through line 93 to the outgoing signal amplifier 89.

The control input signals to the circuits 94 and 100 include a control signal on line 250 which connects the processor circuitry 92 to the switching circuitry 94 as well as to the transmitter section 93; a signal applied through line 327 from the processor circuitry to the switching circuitry 94 to control transmission of tone signals; a signal a line 328 applied from the processor circuitry 92 to the switching circuitry 94 to control transmission of out-going line signals; control signals applied through lines 329 and 330 from the processor circuitry 92 to the circuitry 100; a local answer control signal applied from terminal 18 of the circuit board 60 and through line 331 to the circuitry 100; and control signals applied through lines 332, 333 and 334 from the voice operated control circuits 102 to the circuitry 100. In addition, a ring detect signal is applied from the ring detector and gating circuits 110 and through line 113 to the circuitry 100.

Such applicable control signal operate to control switching of signals within the circuits 94 and 100. In addition, the circuits operate to generate a speaker squelch signal on a line 335 which is connected to terminal 12 of the circuit board 60.

The circuitry 100 includes a summing amplifier 338 which has an output connected to the line 108 and which has three inputs connected to lines 339, 340 and 341. The summing amplifier 338 includes an operational amplifier 342 which has an output connected to the line 108 and through a resistor 343 to a circuit point 344 which is connected through a resistor 346 to a minus input of the amplifier 342. The plus input of the amplifier 342 is connected through a resistor 347 to the +5-volt power supply line 341 and is connected through a capacitor 348 to ground. Circuit point 344 is connected through resistors 350, 351 and 352 and capacitors 353, 354 and 355 to the lines 339, 340 and 341. Line 341 is connected to the movable contact of a potentiometer 356 connected between ground and a line 358.

A second summing amplifier 360 is provided which includes an operational amplifier 361 having an output connected through a capacitor 362 to the line 324 and through a capacitor 363 and a resistor 364 to a minus input of the amplifier 361, a plus input of amplifier 361 being connected to a resistor 365 to the +5-volt supply line 141. The minus input of amplifier 361 is connected through resistors 367 and 368 and capacitors 369 and 370 to lines 371 and 372.

The circuitry 100 further includes two integrated circuits 373 and 374, each of which includes four switch devices. The circuit 373 includes a switch device 375 operative to control transmission of incoming line audio signals from line 109 to line 372 for application to the speaker 61. A control input of device 375 is connected to the output line 332 of the circuitry 102, line 332 being connected through a diode 377 to the local answer control line 331.

The circuit 373 includes a second switch device 378 which has one terminal connected through resistors 379 and 380 to the line 103 and a second terminal connected to the line 98. A control input of the device 378 is connected to the line 334 and through a diode 381 to the local answer control line 331. In a local answer mode of operation, device 378 operates to transmit microphone audio signals to the outside line.

A third device 382 of circuit 373 has one terminal connected to the junction between resistors 379 and 380, a second terminal connected to the line 358, and a control terminal connected to a line 384. Device 382 is used in transmitting microphone audio signals to the summing amplifier 338 for transmission to the handset 12.

A fourth device 386 of circuit 373 has one terminal connected to the line 98 and a second terminal connected to a line 387. A control input of the device 386 is connected through a resistor 389 to ground and through a resistor 390 to line 333. Device 386 is used in transmitting audio signals received from the handset 12 to the outside line.

The second integrated circuit 374 has four switch devices 391-394. Device 391 has one terminal connected to the line 322, to which a tone signal is applied, and a second terminal connected through a capacitor 396 and through the line 325 to the ring select switch 326. Ring select switch 326 includes a movable contact 397 which is illustrated in an off position. In second position, it connects the line 325 through a resistor 398 to the terminal 13 of the circuit board 60, resistor 398 having a relatively high valve to obtain a relatively low amplitude audible tone or ringing signal. In a third position, contact 397 connects line 325 through a resistor 399 to the terminal 13, the resistor 399 having a lower resistance to obtain a higher amplitude audible signal.

The second and third devices 392 and 393 of circuit 374 have terminals connected together to the line 104 which is coupled to the output of the receiver section of the control unit. A second terminal of the device 392 is connected to the line 371 for transmission of audio signals from the handset and through the summing amplifier 360 to the speaker amplifier, in certain modes of operation. A second terminal of the device 393 is connected to the line 387 for transmission of audio signals from the handset and through the device 386 to the out-going line signal amplifier and thence to the outside line. The fourth switch device 394 has one terminal connected to the incoming signal line 109 and a second terminal connected to the line 339 for application through the summing amplifier 338 to the line 108 and for transmission to the handset.

The control inputs of the devices 391-394 are connected to control circuitry including an integrated circuit 400 having four NAND gates 401-404. The output of gate 401 is connected through the line 335 to the terminal 12 of the control circuit board 60, the terminal 12 being a "squelch" terminal and being connected to the base of a control transistor which operates to effectively short-circuit the input of the speaker amplifier when the line 335 is brought high. The two inputs of the gate 401 are connected together and to a line 405 which is connected through a resistor 406 to ground. Line 405 is connected through diodes 408, 409 and 410 to the line 331, the line 384 and a line 411 which is connected to the output of the gate 402 and also to the control terminal of the switch device 391.

One input of the second gate 402 is connected to the ring detect line 113 while the other is connected through the line 329 to an output terminal of the processor circuit 92. The output of the second gate 402 is connected to the switch device 391 to cause transmission of a tone signal when either the ring detect line 113 or the processor line 329 is brought low.

The third gate 403 has its output connected to the line 384 which is connected to the switch devices 392 and 382 to control transmission of audio signals from the handset to the speaker and to control transmission of audio signals from the microphone to the handset. One input of gate 403 is connected to the output of the fourth gate 404. A second input of the gate 403 is connected through line 330 to the processor circuitry 92 which is also connected through a diode 414 to a line 415 which is connected to the control input terminals of switch devices 393 and 394, also through a resistor 416 to the +5-volt power supply line 141 and also through a diode 417 to one input of the fourth gate 404 and also to the line 308. The second input of the gate 404 is connected to the line 331. Line 331 is connected through a resistor 419 to the +5-volt power supply line 141 to be pulled toward a high state. It is also connected through a diode 420 to the line 330 from the processor circuitry 92 and may be brought to a low state when line 330 is brought low or when the local answer switch 70 is in a position as shown in FIG. 5, i.e., when the control unit 11 is not in the local answer mode.

When there is a high 83 Hz tone detect signal on line 308 and the control unit 11 is in the local answer mode, or when the processor line 330 is brought low, the line 384 is high to activate switch devices 392 and 386 for transmission of audio signals from the handset to the speaker and from the microphone to the handset.

Switch device 393 is activated when there is a high 83 Hz tone detect signal on line 308 and the processor line 330 is high. When switch device 386 is also activated as hereinafter described, audio signals are applied from the handset to the outside line.

Switch device 394 is activated for transmission of incoming audio signals from the outside line to the handset except when processor line 330 is brought low.

As shown in FIG. 10, switching circuit 94 includes an integrated circuit 422 with four switch devices 423-426, only three of which are used in the illustrated apparatus. Switch device 423 has one terminal connected to the line 95 and through resistor 427 to ground and a second terminal connected through a resistor 428 to ground and through a capacitor 429 to the line 322. Device 424 has one terminal connected to the line 95 and a second terminal connected through a resistor 430 to ground and to the line 93. Device 426 has one terminal connected to the line 98 and a second terminal connected through a resistor 432 to ground and to the line 97. A control input of the first device 423 is connected through the line 327 to the processor circuitry 92 and a control input of the second device 424 is connected to the line 250. The control input of the device 426 is connected to the line 328.

MICROPHONE AMPLIFIER AND VOICE OPERATED CONTROL CIRCUITRY (FIG. 11)

The circuitry 102 of FIG. 11 is operative in a local answer mode to allow use of both the speaker and the microphone of the control unit in a manner such as to avoid feedback. At the moment that a user speaks into the microphone 101, the circuitry operates to amplify the microphone signal and to immediately deactivate the switch device 375 in the circuitry 100 (FIG. 9) to avoid transmission of the signal from the microphone to the speaker. At the same time, the switch device 378 is activated for transmission of an amplified microphone signal through line 103, and through resistors 380 and 379 to the line 98, for transmission to the outside line. When the user's voice signal is terminated, the circuitry operates after a slight pause of approximately 0.5 seconds to switch back to a condition in which the switch device 375 is activated for transmission of the audio signals from the outside line to the speaker. A delay of approximately 0.5 seconds allows for the shorter pauses which occur during normal speech patterns and prevents continual on-off switching operations. There is, however, a very fast response to the user's voice signal to avoid any loss of speech.

An important feature is that the circuitry so operates as to allow for a three-way conversation, to allow for the user at the control unit to talk to both the user of the handset and the outside party at the same time.

Another feature is that the microphone and speaker of the control unit may be used for intercom communication with the handset.

The output line 333, which opeates through the resistro 390 to control the switch device 386, is coonnected tot eh output of an operational amplifier 436 which is at a high level except at times during local answer operation. The output linne 332, which controls the switch device 375, is connected through a resistor 437 to the output of amplifier 436 and is also connected through the diode 377 to the local answer line 331, diode 377 being in the circuitry 100, shown in FIG. 9. Line 331 is grounded when the control unit is not in the local answer mode and line 332 is held low through diode 377. In the local answer mode, line 331 is at a high level and line 332 may be either pulled to a high level from the output of the amplifier 436 or placed at a low level, depending upon the state of the amplifier 436.

Line 332 is also connected through a resistor 438 to the base of a transistor 439 having a grounded emitter and having a collector connected to the line 334 and also connected through a resistor 440 to the +5-volt supply line 141. Transistor 439 operates as an inverter, the line 334 being in a state opposite that of the line 332.

A positive reference voltage is applied to the plus input of the amplifier 436 from the movable contact of a potentiometer 442 having one terminal connected to ground and a second terminal connected through a resistor 443 to the +10-volt power supply line 139. A resistor 444 is connected between the plus input of amplifier 436 and its output.

The minus input of amplifier 436 is connected through a diode 446 to the local answer line 331 to be grounded except during the local answer mode, the output of amplifier 436 being thereby maintained at a high level except during the local answer mode.

When the control unit is in the local answer mode, the line 331 is at a high level and the minus input of amplifier 436 may be elevated to a potential greater than that of its plus input, in response to an amplified microphone signal. The output of the amplifier 436 is then switched to a low state to deactivate the switch devices 375 and 386 and to activate the device 378, through the line 334.

The minus input of amplifier 436 is connected through a capacitor 448 to ground and through a diode 449 and a parallel resistor 450 to a circuit point 452. Circuit point 452 is connected through resistors 453 and 454 to circuit points 455 and 456 which are at the outputs of two detector circuits. The first detector circuit is responsive to the output signal from the microphone 101 and it develops a positive voltage of the circuit point 455 in proportion to the amplitude of the microphone output signal. The second detector circuit is responsive to a signal from the speaker and it develops a negative voltage at the circuit point 456 which is proportional to the voltage applied to the speaker. Since the voltages developed at circuits points 455 and 456 are of opposite polarity, the voltage at circuit point 452 corresponds to differences between such voltages and, with proper adjustment, the net voltage developed at circuit point 452 may be substantially independent of the intensity of any soundwaves transmitted from the speaker to the microphone 101, to be proportional only to the intensity of the user's voice picked up by the microphone 101.

The voltage developed at circuit point 452 is of positive polarity and it is applied directly through the diode 449 to rapidly charge the capacitor 448 and to increase the potential of the negative input of amplifier 36. When the voltage so developed exceeds the reference voltage applied from the potentiometer 442 to the plus input of amplifier 436, the amplifier 436 is switched to a state in which the output is low, to perform the aforementioned switching operations.

The discharge path for the capacitor 448 is through the resistor 450 which has a resistance which is such in relation to the capacitance of the capacitor 448 as to provide a time constant of substantial magnitude, preferably on the order of 0.5 seconds. This feature provides the aforementioned pause while the diode 449 provides the rapid response to a voice signal from the user.

The microphone signal detector circuit comprises a capacitor 459 and a resistor 460 connected in parallel between circuit point 455 and ground and a pair of diodes 461 and 462 connected in series between circuit point 455 and ground, the junction between diodes 461 and 462 being connected through a capacitor 463 to the output of an operational amplifier 464, a resistor 465 and a capacitor 466 being connected in parallel between the output of amplifier 464 and one input thereof which is connected through a resistor 469 and a series capacitor 470 to the movable contact of a potentiometer 473 which forms a microphone gain control. Potemtiometer 473 is connected between ground and the output of an operational amplifier 474 with a resistor 475 and a capacitor 476 being connected in parallel between the output of amplifier 474 and one input thereof, connected through a capacitor 478 to one terminal of the microphone 101, the other terminal of the microphone 101 being connected to ground. Amplifier 474 amplifies the microphone signal and its output is connected to the line 103.

A second input of the detector signal amplifier 464 is connected to a circuit point 480 connected through a resistor 481 to a circuit point 482 which is connected to the second input of the amplifier 474, also through a capacitor 483 and a resistor 484 to ground and also through a resistor 485 to the +10-volt power supply line 139. The ungrounded terminal of the microphone 101 is connected through resistors 487 and 488 to the +10-volt supply line 139, the junction between resistors 487 and 488 being connected through a capacitor.

The speaker signal detector circuit is similar to the microphone signal detector circuit. A capacitor 491 and a resistor 492 are connected in parallel between circuit point 456 and ground and a pair of diodes 493 and 494 are connected in series between circuit point 456 and ground, the diodes 493 and 494 having a polarity opposite that of the diodes 461 and 462 so as to develop a negative voltage at circuit point 456 rather than a positive voltage as developed at circuit point 455. The junction between diodes 493 and 494 is connected through a capacitor 495 to the output of an amplifier 496. One input of the amplifier 496 is connected to the circuit point 480. The other input thereof is connected through a resistor 497 to its output and through a resistor 498 and a series capacitor 499 to the movable contact of a potentimeter 500 which is connected in parallel with a capacitor 501, between ground and a line 502. Line 502 is connected to terminal 16 of the circuit board 60 which is connected to one terminal of the speaker 61.

INTERRUPT CIRCUITRY (FIG. 12)

The interrupt circuitry 116, shown in FIG. 12, operates to effect a high to low transition of the line 117 and to generate an interrupt in response to either a high to low transition or a low to high transition of a ring detect signal on line 114 or in response to either a high to low or a low to high transition on the line 119. It may also operate to generate an interrupt in response to a high to low transition on a line 506 which is connected to terminal 7 of the circuit board 60 and which is connected to ground when the intercom switch 67 is operated.

The interrupt circuitry includes an operational amplifier 507, which has its output connected to the line 117, also through a resistor 508 to the +5-volt power supply line 141 and through a resistor 509 to the plus input of the amplifier 507. The plus input of amplifier 507 is connected through a resistor 510 to a circuit point 511 which is connected through a resistor 512 to the +5-volt supply line 141. The minus input of amplifier 507 is connected through a resistor 514 to a circuit point 515 which is connected through a resistor 516 to ground. Through the resistors 510, 512, 514 and 516, the amplifier 507 is normally biased to an "ON" condition to develop a high output at the output line 117.

The ring detect signal line 114 and the "SIGNAL PRESENT" line 119 are connected through capacitors 517 and 518 to a circuit point 520 which is connected through diodes 521 and 522 to the plus and minus inputs of amplifier 507, also through a resistor 524 to the circuit point 511 which is connected through a resistor 525 to the circuit point 515. The capacitors 517 and 518 are normally charged at levels corresponding to the levels of the lines 114 and 119. When there is a high to low transition on either of the lines 114 or 119, the positive input of the amplifier 507 is dropped to a low level through the diode 521 to cause a high to low transition at the output line 117. Similarly, when there is a low to high transition on either of the lines 114 or 119, the minus input of amplifier 507 is moved from a low level to a high level to cause a high to low transition on the output line 117.

The line 506 is connected through a resistor 528 to the +5-volt supply line 141 and is connected through a capacitor 529 to a circuit point 530 which is connected through a resistor 531 to the circuit point 511 and which is connected through a diode 532 to the plus input of amplifier 507. When the intercom switch 67 is operated to ground the line 506, a high to low transition of the plus input of amplifier 507 is effected through the diode 552, to generate an interrupt.

PROCESSOR, MEMORY, TONE GENERATOR AND CONTROL CIRCUITRY (FIG. 13)

The processor, memory, tone generator and control circuitry 92, as illustrated in FIG. 13, comprises a microcomputer 536 which may, for example, be a PIC 1670 8-bit microcomputer manufactured by General Instrument Corporation. A real time interrupt input terminal of the microcomputer 536 is connected through a resistor 537 to the 5-volt supply line 141 and is also connected to the collector of a transistor 538, the emitter of which is connected to the line 117. Transistor 538 operates to prevent an interrupt during certain conditions. Its base is connected through a resistor 539 to a circuit point 540 which is connected through the line 320 to the output of the gating circuit 319 of the circuitry 118, shown in block form in FIG. 8. Thus, circuit point 540 is also connected through a diode 541 to a line 542 which is connected to an output terminal of the microcomputer 536. Line 542 is also connected to the incoming signal amplifier 90 and to the ring detector and gating circuits 110.

The circuitry 92 also includes a tone generator 544 which may be a standard type of DTMF integrated circuit having an output terminal connected to the line 95 and having input or control terminals connected through lines 545-552 to output terminals of the microcomputer 536, another terminal of the circuit 544 being connected to the collector of a transistor 544. The emitter of the transistor 554 is grounded and the base thereof is connected through a resistor 555 to the line 327 which is connected to an output terminal of the microcomputer 536. Line 552 is connected through a resistor 557 to the base of a transistor 558 having a grounded emitter and having a collector connected to the line 328 which is connected through a resistor 559 to the +5-volt supply line 141. An oscillator input terminal of the circuit 544 is connected through a capacitor 560 to an oscillator terminal of the microcomputer 536 which is connected through a resistor 561 to one terminal of a crystal 562, the other terminal of crystal 562 being connected to a second oscillator terminal of the microcomputer 536. A pair of capacitors 563 are connected between ground and the terminals of crystal 562 with a resistor 564 connected in parallel with the crystal 562.

Certain of the interconnect lines between the tone generator 544 and the microcomputer 536 are also used in sensing and control of line advance, hold, dial select and program security functions. Lines 545 and 546 are connected to switch contacts which are selectively engageable by a dial select switch contact 566 to be selectively connectable a line 567 which is connected to a terminal of the microcomputer 536 and also to the terminal 6 of the control board 60. Line 547 is connectable through a program security switch 568 to the line 567. Lines 548 and 549 are respectively connected to terminals 4 and 5 of the control board 60 to be connectable to the line 567 through the line advance and hold switch contacts 66 and 65. Line 551 is connected to the line 567 through a diode 570.

To inhibit transmission of audio signals to and from the outside line, an output of the microcomputer 536 is connected to a line 572 which is connected through a diode 573 to the line 328 and through a diode 574 to a line 575. Line 328 controls transmission of audio signals to the input of the outgoing signal amplifier 89 and line 575 controls transmission of audio signals by the amplifier 90.

To control the relay 131 which is used in commercial applications, a terminal of the microcomputer 536 is connected through a line 577 and a resistor 578 to the base of a transistor 580, the collector of which is connected to the relay 131.

For control of the two-line interface circuit 122, a set of terminals U, W, X, and Z are provided, connected to corresponding terminals of the circuit 122, terminal U being connected to line 572 and terminal Y being connected to line 577 with terminals W, X and Z being connected to other outputs of the microcomputer 536.

A non-volatile memory 582 is provided for storing a 3-digit security code and for storing numbers to be automatically dialed. Terminals of the memory 582 are connected through lines 583-586 to terminals of the microcomputer 536 and also through resistors 587-590 to the power supply line 140. Another terminal of the memory 582 is connected through a line 592 to a terminal of the microcomputer 536 and also through a resistor 593 to the collector of a transistor 594 which is connected through a resistor 595 to the power supply line 140. The base of the transistor is connected through a resistor 596 to the line 586. Another terminal of the memory 582 is connected to the line 143 which is connected to a minus 25-volt output of the power supply 136.

SCHMITT TRIGGER CIRCUIT (FIG. 14)

FIG. 14 is a circuit diagram of the Schmitt trigger circuit 318. The output line 120 is connected through a resistor 600 to the +5-volt power supply terminal and is connected to the output of an operational amplifier 601, also through a resistor 602 to the minus input of the amplifier 601, the minus input of amplifier being connected through a resistor 603 to the input line 106, for switching of the amplifier from one state to the other, at switching levels which are dependent upon the voltage level at the input line 106. The switching levels are such that the more positive level is well below the average level of the positive portions of applied pulse-containing signal, the more negative level is well above the average level of the negative portions of the applied pulse-containing signal to minimize the effects of noise and to obtain a "clean" output.

In accordance with an important feature, a variable bias level is applied to the minus input of the amplifier 601, the bias level being changed in proportion to the average integrated value of 98 Hz pulses applied to the line 106.

In particular, the minus input of amplifier 601 is connected through a capacitor 605 to ground and through a resistor 606 to the output of a second operational amplifier 607. The minus input of amplifier 607 is connected to the output thereof and is also connected through a capacitor 608 to a circuit point 609 which is connected through a resistor 610 to the line 106 and through a resistor 611 to the plus input of amplifier 607. The plus input of amplifier 607 is connected through a capacitor 612 to ground and is also connected through a resistor 613 to the movable contact of a potentiometer 614 connected between ground and the +5-volt supply terminal.

In operation, the capacitor 608 and the resistors 610 and 611 cooperate in producing a low pass filter action such that the bias voltage developed at the minus input of the amplifier 601 is proportional to the average integrated value of the applied signal-containing 98 Hz pulses. It has been discovered that the average integrated value of such pulses may vary over a substantial range depending upon the duration of the pulses being transmitted. As a result, the DC level at the input line 106 is varied and the amplifier 607 and associated circuitry balances out this effect to avoid any substantial effect on the triggering operation of the amplifier 601. The overall result is a great improvement in the accuracy of detection of the leading and trailing edges of the 98 Hz pulses, permitting operation even under extremely adverse noise conditions.

By way of example and not by way of limitation, the components of the circuit 318 may have values as follows:

    ______________________________________                                         Reference Numeral     Value                                                    ______________________________________                                         600                   2.2K                                                     602                   1 M                                                      603                   100K                                                     605                   0.001 MFD                                                606                   82K                                                      608                   0.1 MFD                                                  610; 611              220K                                                     612                   0.047 MFD                                                613                   4.7 M                                                    614                   20K                                                      ______________________________________                                    

FIG. 14 also provides a circuit diagram of the gate circuit 319. The minus input of amplifier 601 is connected through a diode 616 to the line 314 which is connected through a resistor 617 to the base of a transistor 618. The emitter of transistor 618 is grounded while the collector thereof is connected to a line 320 and through a resistor 620 to the +5-volt supply terminal.

83 HZ DETECTOR CIRCUIT (FIG. 15)

FIG. 15 is a circuit diagram of the 83 Hz detector circuit 305. The line 306 is connected through a capacitor 622 and a resistor 623 to the minus input of an operational amplifier 624, the minus input being connected through a resistor 625 to the +5-volt power supply terminal and being also connected to a resistor 626 to the output of amplifier 624. The plus input of amplifier 624 is connected through a resistor 627 to the output of an amplifier 628, the plus input of which is connected through a resistor 629 to the +5-volt power supply terminal. A resistor 630 and a capacitor 631 are connected in parallel between the minus input of amplifier 628 and the output thereof. The minus input of amplifier 628 is connected through a fixed resistor 632 and a variable resistor 633 to the output of amplifier 624, which forms an output terminal of the circuit and which is connected through a capacitor 635 and a resistor 636 to a circuit point 637. Circuit point 637 is connected through a diode 638 to ground and is connected through a diode 639 to a circuit point 640 which is connected through a resistor 641 and a parallel capacitor 642 to ground. Circuit point 640 is connected through a resistor 643 to pin 14 of an integrated circuit 644 having another pin 13 connected to the line 308 with a resistor 645 being connected between pins 13 and 14. The detector circuit 305 uses an operational amplifier of the integrated circuit 644 which is a commercially available chip having IF amplifier and detector components used in the receiver section of the control unit 11.

The circuit as shown operates as a very highly selective filter which has an extremely narrow bandpass at the frequency of 83 Hz. As a result, it can operate to detect the 83 Hz signal under very adverse noise conditions.

It is noted that both amplifiers 624 and 628 operate as active filter amplifiers, contributing to the highly selective operation of the filter. The skirts of response continuously fall at 6 dB/octave, with an ultimate rejection which greatly surpasses the 30 to 40 dB rejection of standard OR-Amp bandpass circuits. At the same time, a minimum number of parts is required.

It is important that the proper relative circuit values can be used and by way of example and not by way of limitation, the values of the circuit components may be as follows:

    ______________________________________                                         Reference Numeral     Value                                                    ______________________________________                                         622                   1 MFD                                                    623                   220K                                                     625                   220K                                                     626                   0.015 MFD                                                629                   330K                                                     630                   3.3 M                                                    631                   0.015 MFD                                                635                   0.33 MFD                                                 636                   10K                                                      641                   270K                                                     642                   3.3 MFD                                                  643                   220K                                                     645                   3.3 M                                                    ______________________________________                                    

98 HZ DETECTOR & FILTER CIRCUITS (FIG. 16)

FIG. 16 is a circuit diagram of the 98 Hz detector circuit 312 and the 98 Hz filter circuit 313. The filter circuit 313 has circuitry which is substantially the same as that of the 83 Hz filter circuit 305, including a pair of operational amplifiers 647 and 648 respectively, corresponding to the operational amplifiers 624 and 628, the minus input of amplifier 647 being connected through a resistor 649 and a capacitor 650 to the line 306 and the output of amplifier 647, which forms an output for the filter circuit, being connected through a fixed resistor 651 and a variable resistor 652 to the minus input of amplifier 648. The values of the circuit components may preferably be the same as those listed above for the corresponding components of the 83 Hz filter circuit 305, except that the fixed resistor 651 may have a resistance of 100K, rather than 150K as listed for the resistor 632, and a resistor 653, between the plus input of amplifier 648 and the power supply terminal, may have a resistance of 220K, rather than 330K as listed for the corresponding resistor 629.

It is noted that as shown in FIG. 16, a pair of oppositely poled diodes 655 and 656 are connected in parallel and in series with a capacitor 657 between the line 306 and ground. These components operate in conjunction with the resistor 307 to provide a filtering action with respect to both the 83 Hz and 98 Hz filters. The capacitor 657 may have a value of 1 MFD while the resistor 307 may have a value of 2.2K.

The 98 Hz detector 312 comprises an operational amplifier 659 having an output connected to line 314 and having a minus input connected through a resistor 660 to the +5-volt terminal. The plus input of amplifier 659 is connected through a resistor 661 to a circuit point 662 which is connected through a resistor 663 to the line 314 and to ground through a capacitor 665 and a resistor 666 in parallel. Circuit point 662 is connected through a diode 667 to a circuit point 668 which is connected through a diode 669 to ground and through a capacitor 670 and a resistor 671 to the output of the 98 Hz filter circuit 313.

By way of example and not by way of limitation, the circuit components may have values as follows:

    ______________________________________                                         Reference Numeral     Value                                                    ______________________________________                                         660                   3.3 M                                                    661                   220K                                                     663                   3.3 M                                                    665                   0.22 MFD                                                 666                   220K                                                     670                   0.33 MFD                                                 671                   10K                                                      ______________________________________                                    

GATE CIRCUIT (FIG. 17)

FIG. 17 is a circuit diagram of the gate circuit 310 which comprises an operational amplifier 674 having an output connected to the line 119, having a plus input connected through a resistor 675 to the +5-volt supply and having a minus input connected through a resistor 676 to the line 314 and through a resistor 677 to the line 308. Resistor 675 may have a value of 1M while resistors 676 and 677 may each have a value of 220K.

LINE CIRCUIT (FIG. 18)

FIG. 18 is a circuit diagram of line circuit 86. A transformer 680 is provided having windings 681 and 682. Winding 681 is connected to the lines which are connected through capacitors 683 and 684 to ground. One terminal of the winding 682 is connected through a Zener diode 685 to ground and also to a circuit point 686 which is connected through a capacitor 687 to ground and through a resistor 688 to the +5-volt supply. Circuit point 686 is additionally connected to the collector of a transistor 690, the base of which is connected to the output of the outgoing signal amplifier 89. The emitter of the transistor 690 is connected to a circuit point 691 which is connected to an impedance network including a resistor 692 connected between circuit point 691 and ground. The impedance network further includes a resistor 693 connected between circuit point 691 and a circuit point 694 which is connected to ground through a resistor 695 and a parallel inductor 696. Circuit point 694 is also connected through a variable resistor 697 to a circuit point 698 which is connected through a capacitor 699 to the input of the incoming signal amplifier 90 and through a resistor 700 to a circuit point 701 which is connected to one terminal of the winding 682. Circuit point 701 is connected through a Zener diode 702 to ground and through a capacitor 703 to ground. It is also connected to the collector of a transistor 704 which has an emitter connected to ground through resistors 705 and 706. The base of transistor 704 is connected through a resistor 707 to the circuit point 691 and is connected to the circuit point 701 through a capacitor 708 and a series resistor 709.

In the operation of the circuit, the incoming signal amplifier 90 receives a signal component from the outgoing signal amplifier 89 of one phase, applied from circuit point 691 and through resistor 693 and variable resistor 697 to the circuit point 698. A signal of the opposite phase is applied from the collector of transistor 704 which operates as a phase inverter. By selection and adjustment of the values of the components, a balance is obtained to avoid any coupling from the output of the outgoing signal amplifier 89 to the input of the incoming signal amplifier 90.

The provision of the inductor 696 and associated resistors 693, 695 and 697 is important in providing the proper balance with respect to the reactance of the transformer 680. With the circuit as shown, it is possible to obtain a balance over a quite broad frequency range and to thereby minimize any coupling from the output of the outgoing signal amplifier 89 to the input of the incoming signal amplifier 90. At the same time, efficient coupling is obtained with respect to transmission of signals from the outgoing signal amplifier 89 to the telephone line and transmission of incoming signals from the telephone line to the input of the incoming signal amplifier 90.

By way of illustrative example and not by way of limitation, the components of the line circuit may have values as follows:

    ______________________________________                                         Reference Numeral    Value                                                     ______________________________________                                         683, 684             0.001 MFD                                                 688                  10 Ohm                                                    687                  470 MFD                                                   692                  100 Ohm                                                   693                  330 Ohm                                                   695                  8.2 Ohm                                                   696                  27 Millihermies                                           697                  1K                                                        697                  .2 MFD                                                    700                  22K                                                       703                  0.047 MFD                                                 705                  82 Ohm                                                    706                  68 Ohm                                                    707                  680 Ohm                                                   708                  47 MFD                                                    706                  1K                                                        ______________________________________                                    

The resistor 695 is adjustable to obtain a balance which is as accurate as possible over the audio range of frequencies transmitted.

POWER SUPPLY CIRCUIT (FIG. 19)

FIG. 19 is a circuit diagram of the power supply circuit 136. The line cord 137 is connected to the primary winding of a transformer 712 which has a center-tapped winding section connected through rectifier diodes 713 and 714 and through a fuse 715 to a circuit point 716 which is connected to ground through a capacitor 717, the center tap of the winding section being connected to ground so as to provide a full-wave rectifier circuit. A +10-volt unregulated voltage is developed at the circuit point 716 which is connected to the line 140. The +5-volt regulated voltage on line 141 is produced by a regulator 718 connected through a resistor 719 to the circuit point 716. To develop the +10-volt regulated voltage on line 139, it is connected through a resistor 721 to the circuit point 716 and it is also connected through a Zener regulating diode 722 and a parallel capacitor 723 to ground.

To provide a minus 25 volt signal on line 143, the transformer 712 includes an additional winding section having one end connected to one end of the aforementioned center-tapped section and having an opposite end connected through a diode 725 to a circuit point 726 which is connected to the collector of a transistor 727 operative as a voltage regulator. The base of the transistor 727 is connected through a 27-volt Zener diode 728 to ground and is also connected through a resistor 729 to the circuit point 726. A capacitor 730 and a parallel resistor 731 are connected between circuit point 726 and ground.

The emitter of the regulator transistor 727 is connected through a capacitor 732 to ground and is also connected to the emitter of a transistor 734 operative as a switching device, the collector of transistor 734 being connected to the line 143. The base of the transistor 143 is connected through a resistor 736 to the emitter thereof and is also connected through a resistor 737 and a 27-volt Zener diode 738 to the collector of a transistor 740 which controls operation of the switching transitor 734. The emitter of the control transistor 740 is connected through a capacitor 741 to ground and to a circuit point 742 which is connected through a resistor 743 and a diode 744 to the circuit point 716, i.e., to the +10-volt unregulated output of the supply. The base of the transistor 740 is connected through a resistor 745 to the circuit point 742 and is connected through a resistor 747 and a 9.1 volt Zener diode 748 to ground. Transistor 740 operates to control the switching transistor 734 to supply an enabling signal to the non-volatile memory 582 at a certain time after connection of the primary of transformer 712 to an AC supply. The circuit also operates to disable the non-volatile memory 582 at a certain time after the primary of transformer 712 is disconnected from the AC supply.

Another circuit is provided for controlling application of an initialization signal to the line 142 which is connected to a "MASTER CLEAR" terminal of the microcomputer 536. The line 142 is connected through a pair of parallel reversely poled diodes 749 and 750 to a circuit point 752 which is connected through a diode 753 to the +5-volt supply line 141 and through a resistor 754 to ground. Circuit point 752 is also connected through a resistor 755 to the collector of a transistor 756, the emitter of which is connected to the circuit point 742. The base of transistor 756 is connected through a resitor 757 and a series Zener diode 758 to ground, through a capacitor 759 to ground and through a resistor 760 to the circuit point 742. The Zener diode 758 may be a 7.5 volt diode.

The circuitry operates to apply an initialization signal on the line 142 at a certain time after connection of the primary winding 712 to the AC supply line. This time is after application of V+ to the microcomputer 536 and is before application of enabling signal on line 143 to the non-volatile memory 582. This sequence is found to be very important to obtain the proper initialization operation. As hereinafter described, signals stored in the non-volatile memory circuit 582 may be transferred to a random access memory of the microcomputer 536 during an initialization sequence.

On power-down, i.e., when the primary of transformer 712 is disconnected from the AC supply, the sequence is reversed, the enabling signal being removed from the line 143 to disable the memory before removing signals from the microcomputer circuitry.

By way of example and not by way of limitation, the various components of the power supply circuitry may have values as follows:

    ______________________________________                                         Reference Numeral     Value                                                    ______________________________________                                         717                   2200 MFD                                                 719                   27 Ohm                                                   721                   330 Ohm                                                  723                   10 MFD                                                   729                   10K                                                      730                   220 MFD                                                  731                   1 M                                                      732                   2.2 MFD                                                  736, 737              10K                                                      741                   47 MFD                                                   743                   2.2K                                                     745                   100K                                                     747                   4.7K                                                     754                   100K                                                     755                   22K                                                      757                   4.7K                                                     759                   0.22 MFD                                                 760                   100K                                                     ______________________________________                                    

RING DETECT & TWO LINE INTERFACE CIRCUITS (FIG. 20)

FIG. 20 is a circuit diagram of the ring detection and gating circuit 110 and of the two-line interface circuit 122. The interface circuit 122 is designed for optional use. When used, the jumpers 123 and 124, indicated in dotted lines, are not used and also the jumpers between jacks 87 and 88, indicated by dotted lines 125-128, are not used. A pair of lines 771 and 772, which are connected through the relay contact 130 to the line circuit transformer, are connected to movable contacts 773 and 774 of a relay 776, the contacts 773 and 774 being selectively engageable either with a pair of contacts 777 and 778 or with a pair of contacts 779 and 780. The relay 776 has an operating coil 781 which is energized through a transistor 782. Transistor 782 is biased toward a non-conductive state and may be rendered conductive by a low signal applied to an "X" terminal 783 which is connected through a resistor 784 to the base of the transistor 782. With relay coil 781 de-energized, the lines 771 and 772 are connected through the contacts 773 and 774 to the contacts 777 and 778 to be connected to the "T" and "R" terminals of the jack 87. When the relay coil 781 is energized, lines 771 and 772 are connected to the "T" and "R" terminals of the jack 88.

A pair of relays 787 and 788 are provided having coils 789 and 790 and having contacts 791 and 792, contact 791 being connectable in series with a resistor 793 between the terminals 777 and 778 while contact 792 is connectable in series with a resistor 794 between contacts 779 and 780. The coils 789 and 790 are energized through transistors 795 and 796 which have base electrodes coupled to "U" and "W" terminals 797 and 798 to be energized when such terminals are brought low.

A pair of quad NOR gate circuits 799 and 800 are provided having inputs connected to the terminals 783, 797 and 798 and to other components of the circuitry in the manner as shown, an output of one gate of the circuit 799 being connected to the terminal 1 of the printed circuit board 60, for energization of the "LINE 1" signal light 19 and an output of one gate of the circuit 800 being connected to terminal 2 of circuit board 60 for energization of the "LINE 2" signal light 20. Inputs of gates of the circuit 800 are also connected to "Y" and "Z" terminals 801 and 802.

A ring detector circuit 804 is provided in the interface circuit 122 which has input lines connected to the terminals 779 and 780 of the relay 776. An output line 805 of circuit 804 is connected to an input of a quad NOR gate circuit 806 of the ring detector and gating circuits 110 of the control unit. Another ring detector circuit 808 is provided in the circuits 110, located within the control unit, the output of the circuit 808 being connected to the line 805 and the input thereof being connected to the "T" and "R" terminals of the jack 87. Thus, ring detector circuit 804 of the interface circuit 122 detects an external ring on the "T" and "R" lines of jack 88 while the ring detector circuit 806 within the control unit detects an external ring on the lines connected to the "T" and "R" lines connected to jack 87.

The quad NOR gate circuit 806 is connected as shown. The output of one of the gates is connected to the line 113 which is connected through a resistor 809 to a circuit point 810 which is connected through a capacitor 811 to ground. A diode 813 and a resistor 814 are connected in series with each other and in parallel with resistor 809. Inputs of another gate of the circuit 806 are connected through a line 815 and a diode 816 (FIG. 13) to the microcomputer 536.

The system will respond to interrupts generated by ring signals on either outside line. It also operates through the microcomputer 536 to control the relays of the interface circuit and to obtain line advance and hold operations as well as pulse dialing operations.

MICROCOMPUTER (FIG. 21)

FIG. 21 is a block diagram of the microcomputer 536 which as aforementioned may, for example, be a "PIC 1670" 8-bit microcomputer manufactured by General Instrument Corporation. The functional blocks are connected by an 8-bit bi-directional bus. There are sixty-four 8-bit registers of which the first sixteen are special purpose and there is an arithmetic logic unit and a ROM with 1024×13-bit words. The first sixteen registers are operational registers and they include real-time clock counters A and B, four I/O registers, two status registers, a program counter and a file select register. The remaining registers are general purpose registers which are used for data and control information under command of the instructions.

The operational registers or "files" are designated as follows, it being noted that an octal numbering system is used:

FO--not a physical register; FO calls for the contents of a file select register (F4) to be used to select a file for storage or retrieval of data, F4 being used as an indirect address pointer.

F1 is the "W" register --the working register.

F2--the program counter --points to the next program ROM address to be executed.

F3--the arithmetic status register. The bits of this register are used as follows:

Bit 0 (C)--the carry flag.

Bit 1 (DC)--the half-carrier or decimal carry, used to indicate a carry from bit 3 in the arithmetic logic unit as the result of an addition. This bit is used in the decimal adjust instruction to allow BCD decimal addition.

Bit 2 (Z)--the zero flag which is set to a 1 if the results of the previous operation was identically zero.

Bit 3 (0)--bit 3 is the overflow flag and is set to 1 by operation which cause a signed two's complement arithmetic overflow.

Bit 4 (A8)--bit 4 is the ninth of the program, a read only bit.

Bit 5 (A9)--bit 5 is the tenth bit of the program counter, also a read only bit.

F-4--The file select register.

F-5--The interrupt status register; bits 7-0 being respectively designated as follows: "X", "CNTE", "A/B", "CNTS", "RTCIR", "XIR", "RTCIE" and "XIE".

F-6, 7--"RTCCA" and "RTCCB" which are real-time clock counters which can be arranged as two 8-bit registers, a single 16-bit register or two general purpose registers.

F--10, 11--"I/O PORT A".

F--12, 13--"I/O PORT B".

F--14, 15--"I/O PORT C".

F--16, 17--"I/O PORT D".

It is noted that F--10, 12, 14 and 16 are the "I/O" registers and F--11, 13, 15 and 17 are used for reading the actual pin levels.

The following chart relates the file designations to the pin numbers of the microcomputer 536 (shown in FIG. 13) and also to the reference numerals used in describing the system. Also, the functions of the input or output ports are indicated, where appropriate.

    __________________________________________________________________________     PIN                                                                               FILE I.D. AND/OR        CORRESPONDENCE                                      NO.                                                                               FUNCTION                REFERENCE NO.                                       __________________________________________________________________________     1  OSC                                                                         2  OSC                                                                         3  F10 or F11, 0 "SIGNAL PRESENT"                                                                         119                                                 4  F10 or F11, 1 "KEY CODE IN"                                                                            120                                                 5  F10 or F11, 2 RING DETECT                                                                              114                                                 6  F10 or F11, 3 LINE ADVANCE &                                                                           568                                                    HOLD SW; PROGRAM                                                               SEC.                                                                        7  CLOCK OUT                                                                   8  F10 or F11, 4 HOOK RELAY                                                    9  F10 or F11, 5 AUX. HOOK RELAY                                               10 F10 or F11, 6 INC. SIGNAL AMP.                                                                         542                                                    RING DETECT.                                                                11 F10 or F11, 7                                                               12 F12 or F13, 0 TONEGEN   552                                                 13 F12 or F13, 1 TONEGEN, OR HOLD SW.                                                                     548                                                 14 F12 or F13, 2 TONEGAN", OR LINE ADVANCE                                                                549                                                 15 F12 or F13, 3 TONEGAN,  550                                                 16 F12 or F13, 4 TONEGAN OR DIAL SELECT                                                                   551                                                 17 F12 or F13, 5 TONEGAN OR PROGRAM SEC.                                                                  547                                                 18 F12 or F13, 6 TONEGAN OR DIAL SELECT                                                                   546                                                 19 F12 or F13, 7 TONEGAN OR DIAL SELECT                                                                   545                                                 20 VSS                                                                         21 TEST                                                                        22 F14 or 15, 0 EAROM      592                                                 23 F14 or 15, 1 EAROM      585                                                 24 F14 or 15, 2 EAROM      586                                                 25 F14 or 15, 3 EAROM      584                                                 26 F14 or 15, 4 EAROM      583                                                 27 F14 or 15, 5 EAROM                                                          28 F14 or 15, 6 EAROM                                                          29 F14 or 15, 7 TRANSMITTER                                                                               249                                                 30 F16 or 17, 0 INTERFACE  122                                                 31 F16 or 17, 1 INTERFACE  122                                                 32 F16 or 17, 2 LOCAL ANS. SW.                                                 33 F16 or 17, 3                                                                34 F16 or 17, 4 INTERFACE  122                                                 35 F16 or 17, 5 INTERFACE  122                                                 36 F16 or 17, 6 INTERCOM LIGHT                                                 37 F16 or 17, 7 INTERCOM SW.                                                   38 REAL TIME INTERRUPT     538                                                 39 MASTER CLEAR            142                                                 40 V+                                                                          __________________________________________________________________________

With regard to an external interrupt, the external interrupt request bit (XIR) of F5 is set on any high to low transition of pin 38 to be serviced if the external interrupt enable bit (F5,0) is set or if it set at a later point in the program. Once external interrupt service is initiated, the processor clears the XIR bit, pushes the current program address on to the stack and executes the instruction at address or location 1760 (octal base).

Real-time clock interrupt operation is accomplished with the RTCCA and RTCCB file registers F6 and F7. When timer interrupt service is initiated, the present program counter is pushed onto the stack and the instruction at address or location 1740 is executed.

Each instruction used in the microcomputer of the illustrated embodiment is a 13-bit word divided into an OP code which specifies the instruction type and one or more operands which further specify the operation of the instruction. The following condensed summary lists byte-oriented, bit-oriented and literal and control operations. For byte-oriented instructions, "f" represents a file register designator and "d" represents a destination designator. If "d" is 0, the result is pushed in the "W" register F1. If "d" is one, the result is returned to the file register specified in the instruction. For bit-oriented instructions, "b" represents a bit field designator which selects the number of the bit affected by the operation, while "f" represents the number of the file in which the bit is located. For literal and control operations, "k" represents an eight or nine bit constant or literal value.

    ______________________________________                                                                               Op-                                                                            er-                                      Instruction-Binary(Octal)                                                                     Name         Mnemonic, ands                                     ______________________________________                                         BYTE-ORIENTED INSTRUCTIONS                                                     0 000 000 000 000 (00000)                                                                     No Operation NOP       --                                       0 000 000 000 001 (00001)                                                                     Halt in PIC 1665                                                                            HALT      --                                       0 000 000 000 010 (00002)                                                                     Return from  RETFI     --                                                      Interrupt                                                       0 000 000 000 011 (00003)                                                                     Return from  RETFS     --                                                      Subroutine                                                      0 000 000 000 100 (00004)                                                                     Decimal adjust W                                                                            DAW       --                                       0 000 001 fff fff (00100)                                                                     Move W to file                                                                              MOVWF     f                                        0 000 1d fff fff (00200)                                                                      Subtract W from                                                                             SUBBWF    f,d                                                     file w/borrow                                                   0 000 10d fff fff (00400)                                                                     Subtract W from                                                                             SUBWF     f,d                                                     file                                                            0 000 11d fff fff (00500)                                                                     Decrement file                                                                              DECF      f,d                                      0 001 00d fff fff (01000)                                                                     Inclusive DRW                                                                               IORWF     f,d                                                     with file                                                       0 001 01d fff fff (01200)                                                                     And W with file                                                                             ANDWF     f,d                                      0 001 10d fff fff (01400)                                                                     Exclusive ORW                                                                               XORWF     f,d                                                     with file                                                       0 001 11d fff fff (01600)                                                                     Add W with file                                                                             ADDWF     f,d                                      0 010 00d fff fff (02000)                                                                     Add W to file                                                                               ADCWF     f,d                                                     with carry                                                      0 010 01d fff fff (02200)                                                                     Complement file                                                                             COMPF     f,d                                      0 010 10d fff fff (02400)                                                                     Increment file                                                                              INCF      f,d                                      0 101 11d fff fff (02600)                                                                     Decrement file,                                                                             DECFSZ    f,d                                                     skip if zero                                                    0 011 00d fff fff (03000)                                                                     Rotate file right                                                                           RRCF      f,d                                                     thru carry                                                      0 011 01d fff fff (03200)                                                                     Rotate file left                                                                            RLCF      f,d                                                     thru carry                                                      0 011 10d fff fff (03400)                                                                     Swap upper and                                                                              SWAPF     f,d                                                     lower nibble                                                                   of file                                                         0 011 11d fff fff (03600)                                                                     Increment file,                                                                             INCFSZ    f,d                                                     skip if zero                                                    1 000 000 fff fff (10000)                                                                     Move file to W                                                                              MOVFW     f                                        1 000 001 fff fff (10100)                                                                     Clear file   CLRF      f                                        1 000 010 fff fff (10200)                                                                     Rotate file right/                                                                          RRNCF     f                                                       no carry                                                        1 000 011 fff fff (10300)                                                                     Rotate file left/                                                                           RLNCF     f                                                       no carry                                                        1 000 100 fff fff (10400)                                                                     Compare file to                                                                             CPFSLT    f                                                       W, skip if F W                                                  1 000 101 fff fff (10500)                                                                     Compare file to                                                                             CPFSEQ    f                                                       W, skip if F=W                                                  1 000 110 fff fff (10600)                                                                     Compare file to                                                                             CPFSGT    f                                                       W, skip if F W                                                  1 000 111 fff fff (10700)                                                                     Move file to TESTF     --                                                      itself                                                          BIT-ORIENTED INSTRUCTIONS                                                      0 100 bbb fff fff (04000)                                                                     Bit clear file                                                                              BCF       f,b                                      0 101 bbb fff fff (05000)                                                                     Bit set file BSF       f,b                                      0 110 bbb fff fff (06000)                                                                     Bit test, skip                                                                              BTFSC     f,b                                                     if clear                                                        0 111 bbb fff fff (07000)                                                                     Bit test, skip                                                                              BTFSS     f,b                                                     if set                                                          LITERAL & CONTROL OPERATIONS                                                   1 001 0kk kkk kkk (11000)                                                                     Move Literal to W                                                                           MOVLW     k                                        1 001 1kk kkk kkk (11400)                                                                     Add Literal to W                                                                            ADDLW     k                                        1 010 0kk kkk kkk (12000)                                                                     Inclusive OR IORLW     k                                                       Literal to W                                                    1 010 1kk kkk kkk (12400)                                                                     And Literal and W                                                                           ANDLW     k                                        ______________________________________                                    

FIG. 22 is a memory map showing the use of the general purpose registers as timers and for storage of painters, vectors, flags, key values, security codes and other data used in the system.

FIG. 23 is a general flow chart illustrating the general mode of operation of the processor 536 of the control unit 11. After power-up, initialization operations are performed, including the setting up of various registers or files of the processor either in cleared conditions or in conditions with certain bits in a set condition. The initialization operations are shown in detail in FIG. 31 and the operations may be entered at certain addresses indicated as "STDBY2", "STDBY" and "STDBY1" in the flow charts and also in the listing of the program. For convenience in correlating the flow charts with program listings, which are set forth hereinafter in Tables I and II, the addresses at certain points are indicated in parentheses in the flow charts. It is noted that an octal base numbering system is employed with respect to the addresses and instructions as well as with respect to the files or registers of the system.

After the initialization operations, the operation goes to a "MAIN" operation at address 0267. A talk flag is tested. If it is not clear, indicating that the talk flag is set, the operation goes to certain "KEYRED" and subsequent "KEYTEST", "VERIFY SECURITY" and "REDUNDANT" operations and thence to "TALK JUMP" operations, returning to "MAIN" or to one of the addresses of the initialization operations.

If the talk flag is clear, an escape flag or bit is tested. If the escape bit is not clear, "ESCAPE" operations are performed as indicated by interrupt vectors which may be stored in response to either a timer interrupt or an interrupt generated in response to the detection of an external ring, to the placing of the local answer switch in an "ON" condition or to the transition of a signal received from the handset 12. FIG. 24 illustrates the storage of interrupt vectors in response to interrupts and FIG. 25 illustrates processing of interrupts.

If the escape bit is clear, a "VERIFY SECURITY" flag is tested. If the "VERIFY SECURITY" flag is not cleared, the operation goes to the aforementioned "KEYRED" and subsequent operations. If the "VERIFY SECURITY" flag is cleared, a signal present flag is tested, by testing bit 0 of F11 which corresponds to pin 3 of the processor 536, connected to the line 119. If line 119 is low, indicating the presence of a signal, a "VERIFY SECURITY" flag is set and then the operation proceeds to the "KEYRED" and subsequent operations. If there is no signal present, operations are performed to check the local answer, hold and line advance switches of the control unit 11 and to effect the required operations, with returns as indicated. Such operations are shown in FIG. 32.

Both the "ESCAPE" and "TALK JUMP" operations may use common subroutine or end operations as indicated in the general flow chart of FIG. 23.

The general mode of operation may be clarified by considering the sequences of operations which take place when the system is in a quiescent condition and then considering the operation which takes place in response to placing the control 33 of the handset 12 in a "TALK" position, followed by operation of the keys of the handset to dial a number.

In the assumed quiescent condition, the control unit is energized but the local answer switch of the control unit is off and the switch 33 of the handset in either its "OFF" or "ON" or "STANDBY" positions. In the quiescent condition, the "TALK", "ESCAPE" and "VERIFY SECURITY" flags are all clear and with no signal present, the operation proceeds to a control unit switch-check operation to check the local answer and other switches as shown in detail in FIG. 32. This operation is a "MAIN1" operation, at address 0301, in which a jump vector in F51 is added to the address in the program counter, designated as F2, to jump to a new address. Initially, the vector stored in F51 is 0 and the operation goes to address 0303 and thence to "MJMPO" at address 0306. In "MJMPO", local answer switch is tested by testing bit 2 of F17 which is connected to pin 32 and to terminal 11 of the circuit board 60 which is in a high state normally and which is grounded when the local answer switch is operated to an "ON" condition. In the assumed quiescent condition, bit 2 of F17 is high or not clear and the operation returns to "MAIN" as indicated in FIG. 32.

In the assumed quiescent condition, a timer interrupt is periodically generated and is processed as is shown in FIG. 24. When a timer interrupt is generated, the operation goes to address 1740. Each interrupt causes F34 to be decremented, F34 having been set up with a predetermined count therein during the initialization operations. After repeated interrupts which decrement F34 to 0, F34 is reset and then an intercom flag is tested to determine whether it is in a set condition. If not, a "TALK" mode flag is tested to determine whether it is clear, i.e., whether the system is not in the "TALK" mode. Normally, in the quiescent condition, the "TALK" mode flag will be clear. Then a "VERIFY SECURITY" flag is cleared, after which a "MAIN" vector (0267) is stored in the working register or file W. Then a "CLEARINT" operation is performed in which the vector in W is stored in F23, both interrupts are enabled and the escape bit is set, returning to the point at which the interrupt occurred.

When, after such operations, the operation gets to "MAIN, " the "TALK" flag will be tested and then when the escape bit is tested, it will be found to be set and the operation then goes to an "ESCAPE" operation, at address 0106. In the "ESCAPE" operation, the escape bit is cleared and then the vector in F23 is moved to the program counter F2. In the assumed quiescent condition, the "MAIN" vector is entered into the program counter. Thus, in the assumed quiescent condition, the operation loops from "MAIN" and through tests of the "TALK", "ESCAPE", "VERIFY SECURITY" and "SIGNAL PRESENT" flags and a test of the local answer switch and back to "MAIN", periodically going through the "ESCAPE" operation and directly back to "MAIN" in response to timer interrupts.

If the control 33 of the handset 12 is placed in the "TALK" position, a 83 Hz pilot tone signal is developed and transmitted to be detected in the digital signal detector and processing circuitry 118 of the control unit 11 and to cause the signal present line 119 to be brought low. Line 119 is connected to pin 3 of the processor 536 which corresponds to bit 0 of F11. In the operation as depicted in the basic flow chart of FIG. 23, when the signal present line is brought low, the "VERIFY SECURITY" flag is set and the operation then goes to the "KEYRED" and subsequent operations as depicted in the flow chart of FIG. 26.

KEYRED & RELATED OPERATIONS

Referring to FIG. 26, tests are made to determine the occurrence of a valid transition of the key code input line 120 from a low state to a high state, line 120 being connected to pin 4 which corresponds to bit 1 of F11. To detect such transitions, "SETUP", "INPLO" and "INPHI" subroutines are used. This transition detection operation is a very important feature of the invention and is detailed in FIG. 27, described hereinafter. When a valid low to high transition of the 98 Hz signal is detected, F25 is cleared, F25 being a raw key register, as hereinafter described. After clearing F25, a delay is instituted corresponding to the minimum duration of a valid 98 Hz pulse. At the end of the delay time, F11,1(key code input line 120) is tested to determine whether it is still set or high. If not, it indicates an invalid pulse and the operation returns to "MAIN". If F11,1 remains set, however, a short timer delay is generated and then F11,1 is again tested. If, at this time, F11,1 is clear, it indicates a valid "raw key" pulse of minimum duration which is a pulse referred to hereinafter as a "NULL" pulse.

If, however, F11,1 remains set, F25 is incremented and then if F25 does not contain more than a full count of 23, another short delay is developed and F11,1 is again tested. If the test of the 98 Hz pulse indicates that it is valid, F25 will contain a number corresponding to the duration of the pulse. If the duration of the pulse is less than the minimum valid duration or greater than the maximum valid duration, the operation returns to "MAIN".

Assuming that the pulse is indicated as being a valid "raw key" pulse, the operation proceeds to a "KEYTEST" operation which is complex and which embodies further important features of the invention.

As described in detail hereinafter, the "KEYTEST" operation performs additional validation tests. In general, it tests for receipt of at least a certain number of valid "raw key" pulses of the same duration during receipt of a certain larger number of pulses and stores a validated key value. In the system as illustrated, a validated key value is stored in F40 when six valid "raw key" pulses of the same duration have been received during receipt of a total of not more than eight valid "raw key" pulses. Then a "TONEON" operation is performed, to transmit a 1600 Hz tone to the handset 12 and a "REDUND" flag is set to cause a "REDUND" operation to be performed with respect to valid "raw key" pulses generated in the "KEYTEST" operation.

The "REDUND" operation is also an important feature of the invention. As described hereinafter, the system looks for an acknowledgment signal which the handset transmits in response to the 1633 Hz tone signal. The acknowledgment signal is in the form of a number of valid "raw key" pulses which have a certain value, "null" pulses of minimum duration being used in the illustrated system. The system as illustrated looks for such null pulses and looks for a condition in which, over a period of time, the number of such null pulses less the number of non-null pulses is equal to 8. Then a "TONEOF" operation is performed to terminate transmission of the 1633 Hz signal to the handset 12. Then a "VFYSEC" operation is performed in which the validated key value stored in F40 may be compared with the first digit of a stored security code and verified, if correct.

Another series of 98 Hz pulses may then be transmitted by the handset and the foregoing sequence of operations is repeated, each fully validated key value being compared with a digit of the stored security code, until all digits of the security code have been verified. Then a "VERIFY SECURITY" flag is cleared, a "BEEP" subroutine is called to signal the user of the handset that he is in communication with the control unit. Also, the "TALK" flag is set and a "OFHOOK" subroutine is called, returning to "MAIN". Then, after hearing dial tone, the user of the handset may start keying a number to be called. In response to the validation of a subsequently transmitted key, flags may be conditioned to initiate a talk jump ("TLKJMP") operation, at address 0510.

In the talk jump ("TLKJMP") operation, there is a vectored jump to one of twenty-one addresses, according to an octal base number stored in F32 when the operation is initiated. Under the assumed conditions, a 0 vector is stored and a "TALK" operation is initiated. Initially, the validated key value in F40 is tested to determine whether the key is greater than 10. If not, it is stored in a key queue formed by F60 through F77, and then a dial flag is set and the operation proceeds to a "MANDIL" operation.

In the "MANDIL" operation, F11,3 is tested to determine whether tone or pulse dialing has been selected by the dial select switch 566 and, if pulse dialing has been selected, a further test is made of F11,3 while F12,7 is set, to determine whether 20 pulse per second or 10 pulse per second dialing has been selected. F11,3 and F12,7 correspond to pins 6 and 19 which are connected to contacts of the dial select switch. The "MANDIL" operation functions after such tests to perform tone or pulse dialing operations so as to transmit a keyed digit to the central telephone exchange and also operates to provide proper interdigital timeouts.

During interdigital timeouts, storage operations are performed to store manual dial keys in the non-volatile memory 582 at a "REDIAL" location. Such storage operations are performed in response to timer interrupts. Referring to the interrupt processing flow chart of FIG. 24, the "TALK" flag is set during manual dialing and a "TOUT" vector is stored in F23, to operate in the "ESCAPE" mode to effect a jump to a "TOUT" operation at address 0157. The "TOUT" operation is shown in the flow chart of FIG. 35 and dialed key values are stored in a manner as hereinafter described, for use if a redialing operation is selected.

After transmitting digits to establish communication with a called party through the central telephone exchange, the user of the handset converses with the called party in the normal fashion. The "TALK" flag remains in a set condition and, from "MAIN", the operation goes through the check of the "TALK" flag to "KEYRED", to check for a low-to-high transition of the key code input and, when no transition is detected, back to "MAIN" or to "ESCAPE" if an interrupt has been generated. With the system in the "TALK" mode, a timer interrupt stores the "TOUT" vector in F23 and sets the "ESCAPE" bit (F31,7) to obtain an "ESCAPE" from the "INPLO" or "INPHI" calls in "KEYRED". Under the assumed conditions, the operation returns from "TOUT" to "MAIN", in response to a timer interrupt.

When the user at the handset terminates his conversation, he may move the control 33 from the "TALK" position to the "ON" position or to the "OFF" position. In either case, the loss of signal is detected at the control unit to generate an interrupt. However, the system does not instantaneously switch out of the "TALK" mode. Instead, it conducts tests to make certain that the loss of signal is not a temporary condition. In response to a loss of signal interrupt, a loss-of-signal "LOS" vector is stored in F23. In the subsequent "ESCAPE" operation, a "LOS" counter (F26) and a "LOS" shift register (F27) are used in a manner such as to prevent an effective disconnect from a transient loss-of-signal condition.

TRANSITION DETECTION

As aforementioned, the transition detection operation is an important feature of the invention and is detailed in FIG. 27. The carry flag is cleared, F45 is set up with the binary numbers 00111100 and an "INPLO" test-for-low operation is initiated. After testing the escape flag and finding it clear, a test is made to determine whether the signal is low. If so, F45 is rolled right and, if the carry flag is not set, the operation loops to again roll right if the signal is low and the carry is not set. If the signal remains low during three consecutive tests, the test of the carry flag will show that it is set and the operation then proceeds from the "INPLO" test-for-low operation to the "INPHI" test-for-high operation.

The operation will not proceed to the "INPHI" operation in response to a high signal. However, if during the testing for a low, the signal goes high and the carry is clear, F45 is rolled left and loops back. A roll-right operation is then required to place F45 in the condition it was in before the high signal was detected. Thus, an additional low is required to offset one interjected high and a total of four lows are required to emerge from the "INPLO" test-for-low operation. If there are two interjected highs, a total of five lows are required. Repeated highs have no effect once a carry set condition is established, since the roll-left operation is performed only when carry is clear. When the operaion emerges from "INPLO", it means that at least 3 of the last 5 preceding tests showed lows.

An important feature is that the operation is not adversely affected by variations in the order of receipt of highs and lows during the "INPLO" operation. For example, a high may be detected in the very first test and, if followed by four lows, the operation will proceed to the "INPHI" operation.

The relationship between the number of positive responses and the total number of tests may, of course, be changed. For example, in the illustrated system, F45 may be loaded with binary 00111000, or 00011000 or 00010000 to require greater proportionate numbers of positive responses, when desired.

The system thus allows for the possibility of an interjected negative response such as might be caused by transient noise conditions, for example, without affecting the reliable detection of a valid state. At the same time, it is quite fast in response, and any delay in the response is proportionate to the amount of noise which may be encountered.

The "INPHI" operation is essentially the same as the "INPLO" operation, differing only in that a test is made for a high input, rather than for a low input. With the system, it is possible to operate under extremely high noise conditions and yet obtain a reliable indication of a low-to-high transition.

KEYTEST OPERATION

As aforementioned, the "KEYTEST" operation embodies important features of the invention. This operation tests to see whether six out of a series of not more than eight values are the same. Starting from an initial condition, it examines input key values until obtaining two that are the same. If no two out of the first four consecutive values are the same, the system starts over. If during the first four, two are the same, the system "prepares to go for eight", setting a "PGF8" flag and then after the first four, a "go for eight" or "GF8" flag is set. Once the same value is received six times, it is validated and the system is reset, but if this does not occur after eight values are received, the system starts over.

The "KEYTEST" operation uses F40, F41 and F42 as "buckets" to store validated key values and to also store the number of times that the stored key value has been developed, after an initial reset condition. The key value, designated as k_(m) is stored in the 5 least significant bits of the file in which it is stored while the number of times it has been received, designated as "i_(m) ", is stored in the 3 most significant bits of the file. The current file being tested or used for storage or recall is designated as the "M" file, "M" being 0 when the file is F40, being 1 when the file is F41 and being 2 when the file is F42.

In the "KEYTEST" operation, after a test of the "REDUND" flag and a test for a "NULL" value, "M" is set to 0 and then a test is made of the content of "i_(m) " which is initially F40. Then a test is made of a "GF8" flag which is initially clear and then the contents of F40 and F41 are repectively shifted to F41 and F42 while the validated raw key value in F25 is stored in bits 0-4 of F40. Then a 1 is stored in bit 5 of F40 setting "i_(O) " equal to one.

After setting "i" equal to 1, a key counter "K_(C) " (F46) is incremented and if the total count therein is less than 4, the operation returns to "MAIN". In the next operation, when a test is made to determine whether "i_(m) " equals 0, a negative result is obtained since "i_(m) " is in F40 in this case and F40 now contains a key value. Then a test is made as to whether the key value stored in the current counter is equal to the new key value. If it is, "i_(m) " is incremented and a "PGF8" flag is set after which the key counter "K_(C) " is incremented, returning to "MAIN" if "K_(C) " is less than 4.

If the new key value is not equal to "k_(m) ", the bucket or "M" counter is incremented and if "M" is not equal to 3, the operation returns to address 1205 to test to determine whether "i_(m) " is equal to 0. If so and if the "GF8" flag is not set, the right shift operation is again effected and the new key is dropped into F40, after which "i_(O) " is again set equal to 1. Then the key or "K_(C) " counter is incremented.

If, after incrementing the bucket or "M" counter, it is found that the "i" value in the corresponding file is not 0 but that the key value stored therein is equal to the current key value, the "i" value of the file is incremented. If the "i" values of all three files are not 0 and the "k" values of all three files are not equal to the current key values, "M" will have been incremented to 3 and the key or "K_(C) " count is incremented.

The system as thus far described thus tests the files or "buckets" F40, F41, F42 in order, each file being tested to determine whether it is empty and, if not empty, whether it contains the new key value. When a tested file is empty, a right shift operation is performed first and then the new key value is entered into F40. When the tested file is not empty and it contains the new key, the "i" portion of the tested file is incremented. In either case, the key counter "K_(C) " is incremented. When all three files are not empty and none of them contain the current key value, the key counter "K_(C) " is incremented but the "i" portion of none of the files is incremented.

Both the "GF8" and "PGF8" flags are initially clear or not set and the "GF8" flag is set only after setting of the "PGF8" flag. The "PGF8" flag is set whenever the "i" portion of a tested file is incremented, i.e., whenever two identical key values have been detected. At the end of a key count of 4, if the "PGF8" flag has not been set, the system is reset to the initial condition. If the "PGF8" flag has been set, it is reset and the "GF8" flag is then set. Thereafter, after incrementing "i_(m) ", a test is made as to whether "i_(m) " is equal to 6. If the test shows that it is equal to 6, the key value is validated and is stored in F40, the "REDUND" flag is set and the "TONEON" sub-routine is called. However, if "i_(m) " has not reached 6, another testing operation is made at the end of another 4 key counts, i.e., at the end of a total of 8 key counts. If at the end of 8 key counts, the "i_(m) " test has not shown 6 counts, the system is reset.

The system as shown thus will not produce a validated key value unless at least 6 out of the last 8 preceding values are the same. As a result, the likelihood of an improper validation is extremely small. However, the system will operate under very adverse noise conditions. It is unlikely that transient noise conditions would produce raw key values in F25 and it is extremely unlikely that six out of eight improper key values could be produced. However, the system does allow for the possibility that under high noise conditions, false key values may occasionally be generated. Such false key values may occur at any time during a testing sequence without affecting the operation. Thus, the false key value may be the first value entered after initiating a testing sequence, or both the first and second key values may be false without preventing the production of a validated key value.

It is also noted that the system operates to produce a validated key value when at least "N" out of the last "M" preceding values are the same, "N" being six and "M" being eight in the system as illustrated. However, "N" and "M" may be changed according to the requirements of any particular system, as desired.

REDUNDANT OPERATION

As aforementioned, the system looks for an acknowledgment signal which the handset transmits in response to the 1633 Hz tone signal, the acknowledgment signal being in the form of a series of null pulses, all of which have the same minimum value or duration and which may be described as "redundant" pulses. The system looks for a condition in which, over a period of time, the number of such null pulses, less the number of non-null pulses, is equal to 8. First, a test is made to determine whether the key value stored in F25 is equal to the redundant or "KR" or null value, by testing F25 against itself and then testing the zero flag, F3,2. If a null is detected, F41 is incremented, F41 being now used as a counter. Then F41 is tested to determine whether the count is 8 and if not, the operation returns to "MAIN". The operation also returns to "MAIN" if the test for a null is negative and F41 is in the 0 or reset condition. If the test for a null is negative and F41 is not in a reset condition, F41 is decremented. In order for F41 to reach a full count of 8, there must be a condition in which the accumulated number of null pulses, less the accumulated number of non-null pulses is equal to 8.

When a full count of 8 is reached, files F46 and F47 are cleared and a "TONEOF" sub-routine is called after which a test may be made to make certain that the value in F40 is not a null value. If it is, the operation again goes back to "MAIN", but if not, F41 is cleared and then the operation goes to a "VERIFY SECURITY" operation, "VFYSEC", shown in FIG. 29.

VERIFY SECURITY OPERATION

In the "VERIFY SECURITY" operation, if the "VERIFY SECURITY" flag is not set, F40 is tested to determine whether the key has an off value of 20 or a hook value of 22. If not, the key reject flag (F44,2) is tested, the program proceeding to the "TALK JUMP" operation if the key reject flag is clear. If F40 stores the value of 20, the operation goes to "STANDBY 2" and if the hook value 22 is stored, a "hook" sub-routine is called, the operation then going to "STANDBY 1".

If the "VERIFY SECURITY" flag is set, the operation goes either to a program security operation or to an operation for checking the validity of "KEY VALUE" against the stored security code bytes. After verification of each byte, the security code is shifted for comparison of the validated "T" with the next byte. After verification of three bytes, the system prepares for the talk mode as indicated and then tests the intercom or "ICOM" flag. If the "ICOM" flag is clear, the system calls a "OFHOOK" sub-routine and then goes to "MAIN". Then with the "VFYSEC" flag cleared, the system may respond to a next validated key code input to go to "STDBY2", to call the "HOOK" sub-routine and go to "STDBY1" or, if the key reject flag is clear, to go to "TLKJMP".

TALK JUMP OPERATIONS

In the initial discussion of the operation of the system, a manual dialing example was given, in which it was assumed that the key stored in F40 was equal to zero through #With reference to FIG. 30, if the stored key has a greater number, tests are made to determine the operations to be performed. Thus, if the stored key is an "A" key, the operation goes to a "HOLD" operation at address 1447. If the stored key is a "B" key, a strap is read to determine whether the system is set up for single line or two line operation. If the system is set up for two line operation, the operation goes to a "LINE ADVANCE" operation at address 1504. For single line operation, the corresponding key may be used as a "HELP" key to call the police or another emergency service, for example.

If the key is the intercom key, an "ONHOOK" subroutine is called, F16,3 is cleared and the operation goes to an "ICOMFH" operation at address 337.

If the key has a "NUMBER" greater than that of the intercom key, (greater than 17₈), a jump vector is computed by subtracting 17₈ from the number stored in F40 and the operation goes back to "TLKJMP".

FIGS. 36-42 show details of many of the operations performed after the jump, it being noted that in the operations having lower numbered jump vectors, higher numbers may be stored in F32 to effect jumps to operations having higher vector numbers. The use of the vector jump operation in the "TALK JUMP" and other operations of the system facilitates fast and reliable operation of the system, with minimum memory requirements.

FIG. 43 is a circuit diagram of the microphone amplifier 171, the summing amplifier 172, the 83 Hz filter 177 and the mute circuit 204 of the handset 12, such circuits being shown in block form in FIG. 6. The summing amplifier 172 comprises an op-amp 820 having an output coupled through a capacitor 821 to the modulation signal input line 173 or the transmitter section 148. The input of the op-amp 820 is connected through a capacitor 822 to the output of an OP amp 824 of the microphone amplifier circuit 171, the input of the amplifier 824 being connected through a resistor 825 and a capacitor 826 to a circuit point 827 which is connected to the microphone 17. Circuit point 827 is also coupled through resistors 829 and 830 to the line 174 which is controlled through the control and switching circuitry 152 as hereinafter described.

The input of the summing amplifier 820 is also connected through a capacitor 831 to the line 180 which is controlled by the processor 154 and, in addition, it is connected through a resistor 832 and a capacitor 833 to the line 178 at the input of an integrated circuit 834 in the 83 Hz filter circuit 177. As shown, the line 178 is connected through a capacitor 835 to a circuit point 836 which is connected through a capacitor 837 to an output terminal of the integrated circuit 834 which is connected through a resistor 838 to the line 178. Circuit point 836 is connected through a resistor 839 to ground and through a resistor 840 to the line 176 which is connected to the processor and which supplies an 83 Hz square wave signal to the 83 Hz filter circuit 177.

The mute circuit 204 comprises a resistor 843 connected in series with a diode 844 between the switch 206 and a circuit point 845 which is connected through a diode 846 and a resistor 847 to the line 207. Circuit point 845 is connected through a resistor 848 to the line 205 which is connected to the input of the OP amp 824 of the microphone amplifier 171. When the line 207 is brought high, or when the switch 206 is closed, the microphone amplifier is disabled.

The control and switching circuitry 152 includes a transistor 850 having a collector connected to the line 174 and having an emitter connected to the +5-volt battery line 192. The base of the transistor 850 is connected through a resistor 851 to the line 192 and through a resistor 852 to a line 853 which is connected to an output terminal of the processor 154. Line 853 is also connected through a diode 854 to a circuit point 855 which is connected through resistors 856 and 857 to the input and output of the OP amp 820 of the summing amplifier. When the line 853 is in a high state, the transistor 850 is non-conductive. When the line 853 is brought low by the processor 854, the transistor 850 is rendered conductive to supply an enabling voltage to the transmitter section 148 and also to supply a current through resistors 830 and 829 to the microphone 17.

The line 151, which supplies operating voltage to the receiver section 150, is connected through a capacitor 860 to ground and is connected to the collector of a transistor 861 having an emitter connected through the line 192 to the positive terminal of the battery 190. The base of the transistor 861 is connected through a resistor 862 to the line 192 and is connected through a resistor 863 to the line 159 which is connected to an output terminal of the processor 154. When the line 159 is brought low by the processor 154, the transistor 861 is rendered conductive to supply operating voltage to the receiver section 150. It is also noted that the voltage on line 151 controls application of an output signal from the 1633 Hz detector 156 to an input of the processor 154, connected to a line 865.

As shown in FIG. 43, an integrated circuit 866 has an input connected through the line 157 to the output of the 1633 Hz detector 156 and has an output connected to the line 865. The input and output of the circuit 866 are respectively connected through resistors 867 and 868 to the line 151, for application of appropriate bias and operating voltages to the circuit 866. The circuit 866 may preferably be part of an integrated circuit which also includes detector and IF amplifier circuitry of the receiver section 150, and is in the form of an operational amplifier. The same is true with respect to integrated circuit 834 of the 83 Hz filter circuit 177.

The control and switching circuitry 152 further includes a volume control of the switch device 870 having a terminal 871 connected through a resistor 872 and a capacitor 873 to the receiver output line 155 and having a terminal 874 connected through the line 165 to the input of the amplifier 166, a resistor 875 being connected between terminals 871 and 874 and being shorted out in the "HI" position of the switch device.

The circuitry 152 further includes a switch device 878 which is operated by the "OFF", "ON", "TALK" control 33. The device 878 includes a contact 879 which is connected through the line 192 to the plus terminal of the battery 190 and which is also connected to the emitter of a transistor 880. The collector of transistor 880 is connected through a resistor 881 to ground and is also connected through a line 882 to an output terminal of the processor 154. The terminal 879 is connected to a terminal 883 of the switch device 878 and they are arranged to be connected through a bridging contact, indicated in dotted lines to terminals 884 and 885 in the "TALK" and "ON" or "STANDBY" positions of the control 33. The terminals 884 and 885 and another terminal 886 are connected to the +5-volt switch line 193. In the "OFF" position, terminal 886 is connected to ground.

The base of transistor 880 is connected through a resistor 887 to the emitter thereof and is connected through resistor 888 and a resistor 889 to a terminal of a switch device 878 which is connected to a grounded terminal in the "TALK" position of the control 33. The transistor 880 is then rendered conductive to apply battery voltage to line 882.

The transistor 880 may also be rendered conductive by moving the level of rhe output line 892 of the processor 154 to a low level, line 892 being connected to the junction between resistors 888 and 889. A "PROGRAM SECURITY" switch 894 is connected between line 892 and the line 882. Switch 894 is operated by the code select pushbutton 52, FIG. 3, which may be depressed by using a ballpoint pen with the plate 51 removed.

It is noted that line 892 is connected through a diode 895 and through the line 195 to the charging terminal 84, transistor 880 being rendered non-conductive when terminals 43 and 44 are engaged with the charging terminals 45 and 46 of the control unit 11. With this arrangement, the handset may be left in the "TALK" position and then when it is placed in the cradled position on the control unit, the handset is effectively placed in its "ON" or "STANDBY" condition. The handset may thus be left in the "TALK" position and used as an ordinary telephone to go off or on hook when removing it from and replacing it on the control unit.

The line 882 is connected through a diode 896 to a circuit point 897 which is connected through a capacitor 898 to ground and through a resistor 899 to the line 165. When transistor 880 is rendered conductive, a positive bias voltage is applied to the input of the amplifier 166.

FIG. 44 is a circuit diagram of the battery low detector 144. Two CMOS operational amplifiers 900 and 901 are provided which operate as a switching circuit to be switched from a reset condition to a set condition in response to a battery low condition, the circuit being latched in the set condition until a charging voltage is applied by placing the handset 12 in a cradled position on the control unit 11, to connect the charge terminals or contacts 43 and 44 with the terminals or contacts 45 and 46 of the control unit.

The +5-volt battery line 192 is connected through a resistor 903 to a circuit point 904 which is connected through a resistor 905 to a circuit point 906 which is connected to the input of the amplifier 900. A capacitor 907 is connected between circuit point 906 and the line 192 and a fixed resistor 908 and a variable resistor 909 are connected in series between circuit point 906 and ground. Circuit point 904 is connected through a Zener diode 911 to a circuit point 912 which is connected through a resistor 913 to ground. Circuit point 912 is also connected through a diode 914 to the output of amplifier 901, the input of amplifier 901 being connected through a resistor 915 to the output of amplifier 900.

In operation, the output of the amplifier 901 is normally low, in a reset condition of the circuit, and the diode 914 is conductive, to place the potential of the circuit point 912 close to ground at potential and to develop a certain reference voltage at the circuit point 904, connected to the circuit point 912 through the Zener diode 911. The battery voltage is compared with the reference voltage at circuit point 904 and when the battery voltage drops below a certain level, the circuit is switched to a condition in which the output of amplifier 901 is at a high level. The diode 914 is no longer conductive and the reference voltage at circuit point 904 is raised to a higher level so that the circuit is latched in a condition in which the output is at a high level. When a charging voltage is applied, a reset signal is applied through a diode 917 to the input of amplifier 901.

The processor 154, in the illustrated embodiment, is a "PIC 16C58" microcomputer manufactured by General Instrument Corporation which is similar to that employed in the control unit but which is a CMOS device, having low power dissipation. It also has fewer registers and uses 12-bit instructions, rather than the 13-bit instructions used in the microcomputer of the illustrated embodiment of the control unit. The following condensed summary lists byte-oriented, bit-oriented and lateral and control operations. The designators are the same as in the foregoing condensed summary of operations for the microcomputer of the control unit.

    ______________________________________                                                                               Op-                                                                            er-                                      Instruction-Binary(Octal)                                                                     Name         Mnemonic, ands                                     ______________________________________                                         BYTE-ORIENTED INSTRUCTIONS                                                     000 000 000 000 (0000)                                                                        No Operation NOP       --                                       000 000 fff fff (0040)                                                                        Move W to f  MOVWF     1                                                       (Note 1)                                                        000 001 000 000 (0100)                                                                        Clear W      CLRW      --                                       000 001 1ff fff (0140)                                                                        Clear f      CLRF      f                                        000 010 dff fff (0200)                                                                        Subtract W from f                                                                           SUBWF     f,d                                      000 011 dff fff (0300)                                                                        Decrement f  DECF      f,d                                      000 100 dff fff (0400)                                                                        Inclusive OR W                                                                              IORWF     f,d                                                     and f                                                           000 101 dff fff (0500)                                                                        AND W and f  ANDWF     f,d                                      000 110 dff fff (0600)                                                                        Exclusive OR W                                                                              XORWF     f,d                                                     and f                                                           000 111 dff fff (0700)                                                                        Add W and f  ADDWF     f,d                                      001 000 dff fff (1000)                                                                        Move f       MOVF      f,d                                      001 001 dff fff (1100)                                                                        Complement f COMF      f,d                                      001 010 dff fff (1200)                                                                        Increment f  INCF      f,d                                      001 011 dff fff (1300)                                                                        Decrement f, Skip                                                                           DECFSZ    f,d                                                     if Zero                                                         001 100 dff fff (1400)                                                                        Rotate Right f                                                                              RRF       f,d                                      001 101 dff fff (1500)                                                                        Rotate Left f                                                                               RLF       f,d                                      001 110 dff fff (1600)                                                                        Swap halves f                                                                               SWAPF     f,d                                      001 111 dff fff (1700)                                                                        Increment f, Skip                                                                           INCFSZ    f,d                                                     if Zero                                                         BIT-ORIENTED INSTRUCTIONS                                                      010 0bb bff fff (2000)                                                                        Bit clear f  BCF       f,b                                      010 1bb bff fff (2400)                                                                        Bit set f    BSF       f,b                                      011 0bb bff fff (3000)                                                                        Bit test f, Skip                                                                            BTFSC     f,b                                                     if Clear                                                        011 1bb bff fff (3400)                                                                        Bit Test f, Skip                                                                            BTFSS     f,b                                                     if Set                                                          LITERAL & CONTROL OPERATIONS                                                   000 000 000 101 (0002)                                                                        Return       RETURN    --                                       000 000 0ff fff (0000)                                                                        Tristate port f                                                                             TRIS      f                                        100 0kk kkk kkk (4000)                                                                        Return and place                                                                            RETLW     k                                                       Literal in W                                                    100 1kk kkk kkk (4400)                                                                        Call subroutine                                                                             CALL      k                                        101 kkk kkk kkk (5000)                                                                        Go To address                                                                               GOTO      k                                                       (k is 9 bits)                                                   110 0kk kkk kkk (6000)                                                                        Move Literal to W                                                                           MOVLW     k                                        110 1kk kkk kkk (6400)                                                                        Inclusive OR IORLW     k                                                       Literal and W                                                   111 0kk kkk kkk (7000)                                                                        AND Literal  ANDLW     k                                                       and W                                                           111 1kk kkk kkk (7400)                                                                        Exclusive OR XORLW     k                                                       Literal and W                                                   ______________________________________                                    

The microcomputer includes an arithmetic logic unit which contains one temporary working register or accumulator designated as a "W" register. The microcomputer also includes a set of operational registers or files. A fO register is provided like that of the microcomputer of the control unit, used in conjunction with a file select register, F4. A real-time clock counter register is provided, indicated as F1 and a program counter is provided, designated as F2. A status word register is provided, designated as F3. The "0" bit is a "C" or carry bit; the "1" bit is a "DC" or digit carry bit used in add and subtract instructions and the "2" bit is a "Z" or "0" bit which is set as an arithmetic operation for zero. Bits 3-7 are defined as logic ones. File register F5 is an input register A having operative bits AO-A3, A4-A7 being defined as zeroes. F6 is an input/output register B having 8 bits BO-B7, used for output in the illustrated embodiment.

F7 is an input/output register which is connected to the keyboard 182 in the illustrated embodiment. F1O-F37 are general purpose registers.

The use of the various registers is summarized in the following list:

    ______________________________________                                         File No.              Function                                                 ______________________________________                                          0                    Call of File Select                                      Register (F4)                                                                   1                    Real Time Clock Counter                                   2                    Program Counter                                           3                    Flags                                                     4                    File Select Register                                      5               Port A (Input only)                                                      Bit    Pin     Function                                                        A0      6      163 Detector                                                    A1      7      Both A.sub.1 and A.sub.2                                                       Set=Prog. Sec.                                                  A2      8      A.sub.1 Cl. and A.sub.2                                                        Set=Talk                                                        A3      9      Battery Low                                           6               Port B (I/O used for Output only)                                        Bit    Pin     Function                                                        B0     10      Mute (when set)                                                 B1     11      83 Hz Pilot Tone                                                B2     12      98 Hz Data                                                      B3     13      Tx (off when set)                                               B4     14      Rx (off when set)                                               B5     15      not used                                                        B6     16      Ring output                                                     B7     17      Beep Tone                                             7               Port C (I/O, used for KB input)                               10               Raw keyboard input value                                      11               Key value to X mit                                            12               Key value to X mit (back-up)                                  13               New Key received during X mit                                 14               Key Que                                                       15               "                                                             16               "                                                             17               "                                                             20               "                                                             21               "                                                             22               Key Que and Sec. Code Temp.                                   23               Security Code Save                                            24               Security Code Save                                            25               Que Pointer                                                   26               Temp. key store during X mit and                                               X mit security key time out                                   27               Temp. Port "A" store during                                                    program security                                              30               Output Port "B" save                                          31               Beep counter                                                  32               Loop extend                                                   33               Loop counter                                                  34               Time extend                                                   35               Flags:    Bit   Flags                                                                    0     No key                                                                   1     X mit                                                                          end                                                                      2     Prog.                                                                          Sec.                                                                     3     Key                                                                      4     Battery                                                                        low                                                                      5     Sec. X                                                                         mit                                                                      6     Beep                                                                           tone                                                                     7     Off                                                                            key X mit                                     36               X mit count value                                             37               Timer file                                                    ______________________________________                                    

FIG. 45 is a flow chart illustrating the operation of the handset 12. When the control 33 is placed in the "ON" position, a +5-volt switch voltage is applied through line 193 to the power-up circuit 198 (FIG. 6) which through the line 200 applies a trigger signal to a masterclear input of the microcomputer 154, to go to an address stored at address 777 in the ROM of the microcomputer. In the illustrated embodiment, the stored address is 421 at which a pre-standby or "RSTBY" operation is initiated. The file F6, which is a tristate I/O port is set for output, this being the "B" port which is used for output of the 83 Hz pilot tone signal and the 98 Hz data signal, as well as for control of the transmitter and receiver and for other control and output functions. F7, which is the "C" port used for the keyboard, is set for input. The operation then goes to a "OFF" operation at address 425. An "OFF" code is then stored in F30 and is transferred to F6 to place the transmitter and receiver and other outputs in a "OFF" condition. Then a "BEEP" flag is cleared and a loop counter is then set up and then a test is made to determine whether a battery low signal have been developed at F5,3, i.e, A3 which is connected through line 196 to the output of the battery low detector 144. If a battery low signal is developed, an "OFF3" operation is initiated, going to address 733 to test flags and to initiate signaling operations, returning either to the "OFF" position or to address 431 designated as "RT1". This operation is such as to insure that current consumption is at a minimum, to maintain the security code in memory as long as possible.

If no battery low signal is developed, a "BEEP" counter F31 is set up going to an "OFF1" address 437. Then additional initialization or set up operations are performed and the operation goes to "STBY" and address 451. In the "STBY" operation, F5,1 or "A1" is tested to determine whether the system is in the "ON" or "STANDBY" condition.

If the system is in the standby mode, the mute of the microphone amplifier is activated by setting F6,0 or "BO" high, the receiver is turned on by setting F6,4 or "B4" low and the transmitter is turned off by setting F6,3 or "B3" high. Then after a delay, F33 is decremented. If it is decremented to 0, a battery testing sub-routine "BATEST" is called. If not, a test is made to determine whether a 1633 Hz signal has been received from the control unit 11. This test is made by testing F5,0 or "AO" which is connected to line 865 to the aforementioned circuitry which is connected to the output of the 1633 Hz detector 156.

If the 1633 Hz tone is detected, a signal is transmitted to the ringer speaker, using a "HIT" operation from address 474 to 504, a square wave signal of on the order of 770 Hz being developed at F6,6 or "B6" which is connected through line 166 to the input of the amplifier 162 for the ringer speaker 163. The duration of the ring signal is determined by a number initially stored in F34. Then a delay is obtained by four calls of a "TIME2" subroutine after which the test is again made for the input of the 1633 Hz tone.

If no 1633 Hz tone is detected, a test is made to determine whether the program security switch 894 has been closed, by testing the status of F5,1 and F5,2 or "A1" and "A2" connected to the terminals of the switch. If the test indicates that the program security switch 894 is closed, a "KEY" operation at address 533 is initiated. In this operation, a test is made to determine whether a key has been depressed and if so, whether it is a proper key for entry of a digit of the security code, and if so, the key is decoded and is transmitted to the control unit, using "DECKEY" and "XMTKEY" sub-routines. Proper security code keys are stored in F23 and F24.

If the program security switch 894 is not closed, the operation proceeds to a test to determine whether the control 33 is in the "TALK" position. If it is, the operation proceeds to "TALK" at address 622. If not, the receiver is turned off and a delay is obtained, using a count-down loop operation in which the "A2" and "A1" inputs are checked to determine whether the operation should proceed to "TALK". The receiver is turned off and the current consumption is very low during this delay which is on the order of ten times the duration of the time when the receiver is turned on in the standby loop. As a result, battery life is greatly extended. At the end of the delay time, the operation goes back to "STDBY" at address 451.

The "TALK" operation is shown in the flow chart of FIG. 46. After setting up F32 and F33 which are used in timing loops, the transmitter and receiver are both turned on and the mute is turned off. Then F33, used as another timer-counter is set up, and then a "PILOT" sub-routine is called. The "PILOT" sub-routine at address 324 operates to set and clear F6,1 or "B1" for time periods which are such as to generate the 83 Hz pilot tone.

After generating the pilot tone, security code is output using the operation from address 636 to address 654, with three calls of the "XMTSEC" sub-routine. Then a check is made as to whether it is time to test the battery. If so, the "BATEST" sub-routine is called. If not, a keyboard test and key debounce procedure is followed. If no key has been depressed, and if a check of F5,2 or "A2" shows that the system is still in the "TALK" mode, the "PILOT" subroutine is again called, and after determining whether it is time to check the battery, the keyboard test and key debounce procedure is again initiated. Thus, until a key is depressed, or until the control 33 is switched out of the "TALK" position, the system continuously loops through the keyboard test procedure, periodically checking the battery with the pilot tone being generated during intervals between the status condition checks.

Once a key is depressed and debounced, a "NOKEY" flag is reset and then the key is decoded and stored in transmit and back-up files F11 and F12, after which a "XMITKEY" sub-routine is called and a delay thereafter being generated. If the control 33 should be placed in the standby or "ON" position, the F5,2 or "A2" bit is cleared and then a hang-up procedure is followed. This procedure involves the storage of a hang-up code (20) and the calling of "XMTSEC" and "BEEP" sub-routines. The operation then goes to "OFF" at address 425.

The "XMTKEY" sub-routine starts at address 003. This operation functions to generate 16 pulses at a 98 Hz rate, each pulse having a duration corresponding to a number stored in F11 and also in a back-up file F12. The number of pulses transmitted is determined by storing the octal base number 020 in F36. The time interval from the start of each pulse to the start of the next pulse, i.e. the 98 Hz rate, is determined, in part, by storing the octal base number 024 in F22 which operates as a pilot counter in this operation. Each count corresponds to a time interval of 260 microseconds and after an initial delay of 1.5 milliseconds, F22 is decremented to 0, followed by a delay of 1.45 milliseconds and by other delays such as to obtain a total delay of about 10.2 milliseconds for a 98 Hz rate.

After an initial 1.5 millisecond delay, the pilot count counter F22 is decremented and at the same time, F11, which contains the data to be transmitted, is also decremented, a "LOP1" loop operation being performed until the data-containing file F11 is decremented to 0. Then the data output F5,2 or "B2" is set low to define the end of a pulse, "B2" having been set high prior to the 1.5 millisecond delay. After F11 is decremented to 0, it is restored from the backup file F12 and then decrementing of F22 continues until it is decremented to 0, going to a "GOG" operation for this purpose. After F22 is decremented to 0, operations are performed to test the keyboard and to decode and store keys in the key que files. Also, a test is made to determine whether a 1633 Hz handshake signal has been received, using a "SLO" operation beginning at address 170 which test F5,0 or "AO" which is coupled to the output of the 1633 Hz detector 156. When a key has been received, an audio signal is generated using a "BEEP" sub-routine.

The "XMTKEY" operation is also used during the "XMTSEC" operation after setting timers and the security transmit flag F35,5. During transmission of the security code, the system looks for the transmission of the 1633 Hz handshake signal and operates to transmit the null signals, described in connection with the description of the operation of the microcomputer 536 of the control unit 11.

The "BATEST" sub-routine at address 227 operates when a battery low signal is generated to beep every fifteen seconds for a period of about fifteen minutes and to then beep eight times in rapid sequence and to then place the system in a minimum current drain condition.

The following tables I and II are the aforementioned program listings for the microcomputers 536 and 154, respectively used in the control unit 11 and handset 12 in the manner as described. It will be understood that with other types of microprocessors or microcomputers, other equivalent programs may be used and it will be also understood that the functions and operations performed may be performed in whole or in part through the use of electronic circuitry other than a microcomputer or microprocessor. The system as disclosed in detail, however, has important advantages when a microcomputer or the equivalent is used in achieving highly accurate and reliable response to transmitted and received signals and in using the minimum amount of code in memory. Tables I and II are as follows: ##SPC1## ##SPC2## ##SPC3## ##SPC4## ##SPC5##

It will be understood that modifications and variations may be effected without departing from the spirit and scope of the novel concepts of this invention. 

We claim:
 1. In a cordless telephone system including a handset unit and a control unit each including transmitter means and receiver means for wireless communication between said units, each transmitter means having an audio signal input and each receiver means having an audio signal output, a line circuit in said control unit for connection to at least one outside line and including an input for receiving audio signals to be transmitted to the outside line and an output for transmission of signals received from the outside line, a speaker amplifier in said control unit having an input and an output, a speaker in said control unit connected to said speaker amplifier output, a microphone amplifier in said control unit having an input and an output, a microphone in said control unit connected to said microphone amplifier input, control means in said control unit for operation thereof in a plurality of modes including a "normal" mode and a "local answer" mode, said control means in said "normal" mode being arranged to connect said audio signal output of said control unit receiver means to said input of said line circuit and to connect said output of said line circuit to said audio signal input of said control unit transmitter means while inhibiting transmission of audio signals to and from said speaker amplifier input and said microphone amplifier output, said control means in said "local answer" mode being arranged to connect said line circuit output to said speaker amplifier input and to connect said microphone amplifier output to said line circuit input while inhibiting transmission of audio signals from said audio signal output of said control unit receiver means to said input of said line circuit, voice-operated switching means in said control unit associated with said microphone amplifier and operable in said "local answer" mode, said voice-operated switching means being responsive to microphone-generated audio signals of above a certain threshold value and being then operable to inhibit transmission of audio signals through said speaker amplifier to said speaker.
 2. In a cordless telephone system as defined in claim 1, said control means having an additional "3-way" mode of operation like said "local answer" mode of operation except in being operable to transmit audio signals from said audio signal output of said receiver means of said control unit to said line circuit input and to said speaker amplifier input and to transmit audio signals from said line circuit output and said microphone amplifier output to said input of said control unit transmitter means, said voice-operated control means being operable in said "3-way" mode.
 3. In a cordless telephone system as defined in claim 2, said control means having an additional "intercom" mode of operation, said control means in said "intercom" mode being operable to connect said audio signal output of said receiver means of said control unit to said speaker amplifier input and being operable to connect said output of said microphone amplifier to said audio signal input of said control unit transmitter means of said control unit, said voice-operated control means being operable in said "intercom" mode.
 4. In a cordless telephone system as defined in claim 3, switch means in said control unit for selectively obtaining said "normal", "local answer", "3-way" and "intercom" modes of operation.
 5. In a cordless telephone system as defined in claim 3, said handset unit including means for transmitting control signals to said control unit which include an intercom call signal, and means in said control unit for receiving said intercom call signal and activating intercom call signaling means at said control unit.
 6. In a cordless telephone system as defined in claim 3, means for transmitting control signals from said control unit to said handset unit including intercom call signals, and intercom call signaling means in said handset for operation in response to said intercom call signals from said control unit.
 7. In a cordless telephone system as defined in claim 3, said control unit including hold means for maintaining a connection to an outside line, said control means being operable in said "intercom" mode while said hold means is operable.
 8. In a cordless telephone system as defined in claim 7, a manually operable control at said control unit for controlling said hold means.
 9. In a cordless telephone system as defined in claim 8 means for transmitting control signals from said handset to said control unit including a "hold" signal, and means in said control unit for receiving said "hold" signal and activating said hold means.
 10. In a cordless telephone system including a handset unit and a control unit each including transmitter means and receiver means for wireless communication between said units, each transmitter means having audio and control signal input means and each receiver means having audio and control signal output means, a line circuit in said control unit for connection to at least one outside line and including an input for receiving audio signals to be transmitted to the outside line and an output for transmission of signals received from the outside line, a ring detect circuit in said control unit connected to the outside line for detecting a ring condition of the outside line, speaker and microphone means connectable to said input and output means of said transmitter and receiver means of said control unit for intercom communication with said handset, manually operable intercom switch means on said control unit, control means coupled to said input and output of said line circuit, said input and output means of said transmitter and receiver means of said control unit and said speaker and microphone means of said control unit, said control means including a microprocessor and an interrupt circuit coupled to said microprocessor, to said output means of said receiver means of said control unit, to said ring detect circuit and to said intercom switch means, said interrupt circuit being arranged to apply an interrupt signal to said microprocesor in response to any one of a number of initiating signals including a control signal from said handset unit, a ring detect signal from said ring detect circuit and a signal from said intercom switch means and said microprocessor means being arranged to respond to said interrupt signal to perform control operations in accordance with the status of said control unit and the identity of the signal which initiated said interrupt signal.
 11. In a cordless telephone system as defined in claim 10, said control means being arranged for transmitting a ring signal to said input means of said transmitter means of said control unit for transmission of said handset, said ring signla being transmitted in response to an interrupt generated from said ring detect circuit. 